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Ying Liu

from Lubbock, TX
Age ~40
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Also known as:
Yin G Liu
Related to:
Lixia Li, 61Li LiZou Li, 52Lu P Li, 41Jiaying LiuXinglong Li, 51Ji Liu, 45
Connected to:
Adela Liu, 73Alec X Liu, 39Alpha T Liu, 46Amon Y Liu, 58Andrea Y Liu, 46Anqi Liu, 39Arden K Liu, 64Ba S Liu, 62Bailu Liu, 35Ban Liu, 48

Ying Liu Phones & Addresses

  • Lubbock, TX
  • San Marcos, TX
  • 5720 66Th St, Lubbock, TX 79424 (806) 783-9357

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Graduate or professional degree

Professional Records

License Records

Ying Liu

License #:
31157 - Active
Issued Date:
May 17, 2013
Renew Date:
Dec 1, 2015
Expiration Date:
Nov 30, 2017
Type:
Certified Public Accountant

Ying Liu

License #:
14009 - Active
Issued Date:
Oct 5, 2012
Renew Date:
Jan 1, 2017
Expiration Date:
Dec 31, 2018
Type:
Massage Therapist

Ying Liu

License #:
0402036583
Category:
Professional Engineer License

Ying Liu

License #:
05195 - Active
Category:
Accountants
Issued Date:
Feb 22, 2010
Expiration Date:
Jun 30, 2018
Type:
Certified Public Accountant

Ying Liu

License #:
06149 - Active
Category:
Accountants
Issued Date:
Mar 8, 2012
Expiration Date:
Jun 30, 2018
Type:
Certified Public Accountant

Ying Liu

License #:
03922 - Expired
Category:
Accountants
Issued Date:
Feb 27, 2006
Expiration Date:
Jun 30, 2009
Type:
Certified Public Accountant

Ying Liu

License #:
05195 - Active
Category:
Accountants
Issued Date:
Feb 22, 2010
Expiration Date:
Jun 30, 2018
Type:
Certified Public Accountant

Ying Liu

License #:
06149 - Active
Category:
Accountants
Issued Date:
Mar 8, 2012
Expiration Date:
Jun 30, 2018
Type:
Certified Public Accountant

Medicine Doctors

Ying Liu Photo 1

Ying Liu

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Specialties:
Internal Medicine
Work:
John T Mather Memorial Hospital Internal Medicine Residency
75 N Country Rd, Port Jefferson, NY 11777
(631) 686-2517 (phone), (631) 476-2774 (fax)
Languages:
English
Description:
Dr. Liu works in Port Jefferson, NY and specializes in Internal Medicine. Dr. Liu is affiliated with John T Mather Memorial Hospital.

Lawyers & Attorneys

Ying Liu Photo 2

Ying Liu - Lawyer

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ISLN:
1000807306
Admitted:
2017

Resumes

Resumes

Ying Liu Photo 3

Ying Liu St. Louis, MO

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Work:
University of Missouri - St. Louis

Sep 2006 to 2000
Research assistant
St. Louis Science Center
St. Louis, MO
Aug 2008 to Aug 2010
Staff
Education:
University of Missouri - St. Louis
St. Louis, MO
2006 to 2007
M.A. in Education
Central China Normal University
Wuhan, China
2000 to 2004
B.A. in Education
Ying Liu Photo 4

Ying Liu

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Ying Liu
Managing
KYTE BABY LLC
815 Brazos St STE 500, Austin, TX 78701
Ying Liu
SYT, INC
Ying Po Liu
Incorporator
Todai Corporation
Ying Liu
Secretary
China Carbon Graphite Group, Inc

Publications

Amazon

Dermal Needling Therapy

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This book introduces the fundamentals of dermal needling therapy, such as the principles of treatment, characteristics, indications, management of and precautions with accidents during treatment. It supplies the locations and the indications of commonly-used acupuncture points of the fourteen channe...
Author

Zhang Xue-li, Liu Ying

Binding

Hardcover

Pages

302

Publisher

People's Medical Publishing House

ISBN #

7117106360

EAN Code

9787117106368

ISBN #

15

The Harvard Business School Guide to Careers in Finance, 2002

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The 2002 edition of The Harvard Business School Guide to Careers in Finance is an indispensable resource for anyone considering a job search in finance or investment banking. This all-in-one guide details the trends in finance, describes the industry's vast and varying career opportunities, and prov...
Author

Harvard Business School Press

Binding

Paperback

Pages

130

Publisher

Harvard Business School Press

ISBN #

1578515807

EAN Code

9781578515806

ISBN #

14

Fuzzy Topology (Advances in Fuzzy Systems: Application and Theory)

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Fuzzy set theory provides us with a framework which is wider than that of classical set theory. Various mathematical structures, whose features emphasize the effects of ordered structure, can be developed on the theory. Fuzzy topology is one such branch, combining ordered structure with topological ...
Author

Liu Ying-Ming

Binding

Paperback

Pages

364

Publisher

Wspc

ISBN #

9810228627

EAN Code

9789810228620

ISBN #

7

Paida and Lajin Self-Healing

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Paida and Lajin Self-Healing, authored by Hongchi Xiao, introduces you two “green” self-healing methods — Paida (patting and slapping body areas) and Lajin (stretching tendons) that can help you relieve or even self heal diseases and pains without the worry of side effects. It also reveals some of t...
Author

Hongchi Xiao

Binding

Kindle Edition

Pages

190

Publisher

Hongchi Xiao

ISBN #

1

Good Personality Determines the Whole Life of Children (Chinese Edition)

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This book written by Liu Ying is a necessary guideline for teenagers in their growing course. It helps them face the physical and psychological changes during the in adolescence properly, develop the consciousness of respecting equality when making friends, and undertake the due moral and social re...
Author

Liu Ying

Binding

Paperback

Pages

201

Publisher

Hunan science and Technology Press

ISBN #

7535775802

EAN Code

9787535775801

ISBN #

5

Nutrition Book for Babies of 0-3 Years (Chinese Edition)

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0 -3 years is a critical period for the development of babies, balanced and comprehensive nutrition can provide important protection. According to physical development and nutritional needs of babies of 0 -3 years, the first part introduces the nursing care and feeding guidelines for the parents, an...
Author

Liu Ying

Binding

Paperback

Pages

196

Publisher

Chemical Industry Press

ISBN #

7122158721

EAN Code

9787122158727

ISBN #

4

Us Patents

Apparatus For Measuring Capacitance Of A Semiconductor Device

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US Patent:
6731129, May 4, 2004
Filed:
Dec 17, 2002
Appl. No.:
10/322074
Inventors:
Wendy Ann Belluomini - Austin TX
Chandler Todd McDowell - Austin TX
Sani Richard Nassif - Austin TX
Ying Liu - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3128
US Classification:
324765, 324769, 324763, 324678
Abstract:
An apparatus for measuring capacitance of a semiconductor device is disclosed. The apparatus includes a signal source circuit, a first transistor, a second transistor, and bypass capacitor. The first transistor is connected in series with the second transistor, and the second transistor is connected in series with a device under test. The bypass capacitor connected in parallel with the first and second transistors. Coupled to the first and second transistors, the signal source circuit generates a first signal and a second signal to alternately turn on said first and second transistors such that a discharge current is generated to flow through the first and second transistors.

Method For Determining The Leakage Power For An Integrated Circuit

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US Patent:
6842714, Jan 11, 2005
Filed:
Aug 22, 2003
Appl. No.:
10/646426
Inventors:
Emrah Acar - Austin TX, US
Anirudh Devgan - Austin TX, US
Ying Liu - Austin TX, US
Sani R. Nassif - Austin TX, US
Haihua Su - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 2100
G06F 1900
G06F 1500
US Classification:
702136, 702 60, 702 64
Abstract:
A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.

Method For Estimating Propagation Noise Based On Effective Capacitance In An Integrated Circuit Chip

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US Patent:
7346867, Mar 18, 2008
Filed:
Feb 1, 2005
Appl. No.:
11/048422
Inventors:
Haihua Su - Austin TX, US
David J. Widiger - Pflugerville TX, US
Ying Liu - Austin TX, US
Byron L. Krauter - Round Rock TX, US
Chandramouli V. Kashyap - Round Rock TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

Active Cancellation Matrix For Process Parameter Measurements

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US Patent:
7394276, Jul 1, 2008
Filed:
Jan 17, 2006
Appl. No.:
11/333612
Inventors:
Fadi H. Gebara - Austin TX, US
Ying Liu - Austin TX, US
Jayakumaran Sivagnaname - Austin TX, US
Ivan Vo - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/26
US Classification:
324765, 324769
Abstract:
An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.

Method And Apparatus For Statistical Cmos Device Characterization

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US Patent:
7397259, Jul 8, 2008
Filed:
Apr 17, 2007
Appl. No.:
11/736146
Inventors:
Kanak B. Agarwal - Austin TX, US
Jerry D. Hayes - Georgetown TX, US
Ying Liu - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/26
G01R 33/00
G01R 31/02
US Classification:
324760
Abstract:
A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

Method And Apparatus For Measuring Device Mismatches

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US Patent:
7408372, Aug 5, 2008
Filed:
Jun 8, 2006
Appl. No.:
11/422913
Inventors:
Kanak B. Agarwal - Austin TX, US
Ying Liu - Austin TX, US
Chandler T. McDowell - San Jose CA, US
Sani R. Nassif - Austin TX, US
James F. Plusquellic - Owing Mills MD, US
Jayakumaran Sivagnaname - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/26
US Classification:
324765, 324769
Abstract:
A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

Dynamic Power And Clock-Gating Method And Circuitry With Sleep Mode Based On Estimated Time For Receipt Of Next Wake-Up Signal

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US Patent:
7487374, Feb 3, 2009
Filed:
Jan 13, 2005
Appl. No.:
11/034556
Inventors:
Ying Liu - Austin TX, US
Jente B. Kuang - Austin TX, US
Hung C. Ngo - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/32
US Classification:
713323, 713320
Abstract:
Power-gated circuitry is put in a “sleep mode” that selectively gates both the power supply rails for static power control and the clock distribution for dynamic power control. A time interval M is established following a wake-up signal that includes the time to power-up, perform a computation, and return a result to the following circuitry. Likewise, a time interval N is established that indicates how long to wait after a result is returned before the power-gated circuitry is returned to the sleep mode to assure a desired performance. When a power-gated circuit is going to be needed for a future computation, it is issued a wake-up signal and a predetermined estimated time K for receipt of a next wake-up signal. A decision is made by analyzing the times M, N, and K as to when to return a power-gated circuit to the sleep mode following activation by a wake-up signal.

Method And Apparatus For Measuring Device Mismatches

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US Patent:
7622942, Nov 24, 2009
Filed:
Jun 26, 2008
Appl. No.:
12/147024
Inventors:
Kanak B. Agarwal - Austin TX, US
Ying Liu - Austin TX, US
Chandler T. McDowell - San Jose CA, US
Sani R. Nassif - Austin TX, US
James F. Plusquellic - Owing Mills MD, US
Jayakumaran Sivagnaname - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/26
US Classification:
324765, 324769
Abstract:
A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

Isbn (Books And Publications)

Sprache, Verstehen, Und Ubertragung: Hermeneutische Grundlage Der Philosophischen Ubersetzung

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Author

Ying Liu

ISBN #

3631313918

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Ying Liu from Lubbock, TX, age ~40 Get Report