Yi I Luo

6691216, Feb 10, 2004

Oct 24, 2001

10/004492

Kenneth C. Kelly - Richmond TX
Irvinderpal S. Ghai - Missouri City TX
Jay B. Reimer - Houston TX
Tai Huu Nguyen - Houston TX
Harland Glenn Hopkins - Missouri City TX
Yi Luo - Stafford TX
Jason A. T. Jones - Houston TX
Dan K. Bui - Sugarland TX
Patrick J. Smith - Houston TX
Kevin A. McGonagle - Sugarland TX

Texas Instruments Incorporated - Dallas TX

G06F 1578

711167, 711152, 713502, 710305, 709212

A multi-core DSP device includes a shared program memory to eliminate redundancy and thereby reduce the size and power consumption of the DSP device. Because each of the program cores typically executes the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory couples to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data is preferably stored in separate memory arrays local to the processor core subsystems and accessible by the processor cores via a dedicated data bus. In one specific implementation, the program memory includes a wrapper that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of each clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption may be advantageously reduced.

6892266, May 10, 2005

Nov 8, 2001

10/008696

Jay B. Reimer - Houston TX, US
Harland Glenn Hopkins - Missouri City TX, US
Tai H. Nguyen - Houston TX, US
Yi Luo - Stafford TX, US
Kevin A. McGonagle - Sugarland TX, US
Jason A. Jones - Houston TX, US
Duy Q. Nguyen - Austin TX, US
Patrick J. Smith - Houston TX, US

Texas Instruments Incorporated - Dallas TX

G06F013/14

710305, 710308, 710309

A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

6895479, May 17, 2005

Nov 8, 2001

10/008515

Jay B. Reimer - Houston TX, US
Tai H. Nguyen - Houston TX, US
Yi Luo - Stafford TX, US
Harland Glenn Hopkins - Missouri City TX, US
Dan K. Bui - Sugarland TX, US
Kevin A. McGonagle - Sugarland TX, US

Texas Instruments Incorporated - Dallas TX

G06F012/14
G06F012/00

711152, 711147, 711150, 711168, 712 35, 709213

A multi-core digital signal processor is disclosed having a shared program memory with conditional write protection. In one embodiment, the digital signal processor includes a shared program memory, an emulation logic module, and multiple processor cores each coupled to the shared program memory by corresponding instruction buses. The emulation logic module preferably determines the operating modes of each of the processors, e. g. , whether they are operating in a normal mode or an emulation mode. In the emulation mode, the emulation logic can alter the states of various processor hardware and the contents of various registers and memory. The instruction buses each include a read/write signal that, while their corresponding processor cores are in normal mode, is maintained in a read state. On the other hand, when the processor cores are in the emulation mode, the processor cores are allowed to determine the state of the instruction bus read/write signals. Each instruction bus read/write signal is preferably generated by a logic gate that prevents the processor core from affecting the read/write signal value in normal mode, but allows the processor core to determine the read/write signal value in emulation mode.