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Yeung Au Phones & Addresses

  • Federal Way, WA
  • Beaverton, OR
  • Portland, OR
  • Boston, MA
  • Seattle, WA
  • Antioch, CA
  • Sioux City, IA
  • Kiona, WA

Publications

Us Patents

Self-Aligned Barrier And Capping Layers For Interconnects

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US Patent:
20110163062, Jul 7, 2011
Filed:
Oct 20, 2010
Appl. No.:
12/908323
Inventors:
Roy G. GORDON - Cambridge MA, US
Harish B. BHANDARI - Boston MA, US
Yeung AU - Belmont MA, US
Youbo LIN - Medford MA, US
International Classification:
H05K 3/22
H05K 3/00
C25D 5/02
US Classification:
216 13, 427 962, 205122
Abstract:
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.

Self-Aligned Barrier And Capping Layers For Interconnects

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US Patent:
20140045331, Feb 13, 2014
Filed:
Aug 8, 2013
Appl. No.:
13/962856
Inventors:
Harish BHANDARI - Boston MA, US
Yeung AU - Belmont MA, US
Youbo LIN - Medford MA, US
Assignee:
PRESIDENT AND FELLOWS OF HARVARD COLLEGE - Cambridge MA
International Classification:
H01L 21/768
US Classification:
438653
Abstract:
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.

Self-Aligned Barrier And Capping Layers For Interconnects

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US Patent:
20170012001, Jan 12, 2017
Filed:
Jul 11, 2016
Appl. No.:
15/207198
Inventors:
- Cambridge MA, US
Harish B. BHANDARI - Brookline MA, US
Yeung AU - Belmont MA, US
Youbo LIN - Medford MA, US
International Classification:
H01L 23/532
H01L 21/285
H01L 23/522
H01L 21/288
H01L 21/768
H01L 23/528
Abstract:
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.

Self-Aligned Barrier And Capping Layers For Interconnects

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US Patent:
20150325474, Nov 12, 2015
Filed:
Jul 8, 2015
Appl. No.:
14/793872
Inventors:
- Cambridge MA, US
Harish B. BHANDARI - Brookline MA, US
Yeung AU - Belmont MA, US
Youbo LIN - Medford MA, US
International Classification:
H01L 21/768
H01L 21/288
H01L 21/285
Abstract:
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.
Yeung Wan Au from Federal Way, WA, age ~39 Get Report