Yang Wu Phones & Addresses
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626 Kains Ave, Albany, CA 94706 (510) 528-4187
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626 Kains Ave APT D, Albany, CA 94706 (510) 388-8185
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Berkeley, CA
Business Records
Name / Title
Company / Classification
Phones & Addresses
Principal
Poetry Times Inc
Business Services at Non-Commercial Site
Business Services at Non-Commercial Site
35939 Killorglin Cmn, Fremont, CA 94536
Publications
Us Patents
Glitch Power Analysis And Optimization Engine
View pageUS Patent:
20210384901, Dec 9, 2021
Filed:
Jun 29, 2020
Appl. No.:
16/915099
Inventors:
- Plano TX, US
Ping-San Tzeng - Fremont CA, US
Chao-Yung Wang - Taipei, TW
Yang Wu - Los Altos Hills CA, US
Wen Kung Chu - San Jose CA, US
Ping-San Tzeng - Fremont CA, US
Chao-Yung Wang - Taipei, TW
Yang Wu - Los Altos Hills CA, US
Wen Kung Chu - San Jose CA, US
International Classification:
H03K 17/687
G01R 31/317
G01R 31/317
Abstract:
A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin.A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.