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Xin Wu Phones & Addresses

  • 3316 Giovanni Way, Dublin, CA 94568 (925) 875-8255
  • Ahwahnee, CA
  • Lake Forest, CA
  • San Jose, CA
  • Alhambra, CA
  • South El Monte, CA
  • Rosemead, CA
  • Santa Clara, CA
  • Wichita, KS

Professional Records

License Records

Xin Wu

License #:
="20860" - Expired
Issued Date:
Feb 28, 2001
Renew Date:
Jun 1, 2002
Expiration Date:
May 31, 2004
Type:
Certified Public Accountant

Lawyers & Attorneys

Xin Wu Photo 1

Xin Wu - Lawyer

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Address:
Agricultural Bank of China
(108) 510-7178 (Office)
Licenses:
New York - Currently registered 2012
Education:
New York University Law School

Resumes

Resumes

Xin Wu Photo 2

Xin Wu

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Xin Wu Photo 3

Xin Wu

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Xin Wu Photo 4

Xin Wu

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Xin Wu Photo 5

Xin Wu

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Xin Wu Photo 6

Xin Wu

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Location:
United States
Xin Wu Photo 7

Xin Wu Oakland, CA

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Work:
Shanghai Restaurant
Oakland, CA
Sep 2012 to May 2014
Waitress/Cashier

Education:
University of California, Davis
Davis, CA
2012 to 2014
BA in Economics

Business Records

Name / Title
Company / Classification
Phones & Addresses
Xin Wu
President
Hallnacara Tech Inc
18351 Colima Rd, Whittier, CA 91748
1045 E Vly Blvd, San Gabriel, CA 91776
Xin Wu
President
USA Fu Ding Tian Goldland Inc
32013 Merano St, Lake Elsinore, CA 92530
9312 Vly Blvd, Rosemead, CA 91770
1400 S San Gabriel Blvd, San Gabriel, CA 91776
Xin Min Wu
President
TRANS WORLD FREIGHT SYSTEM (LAX), INC
Business Services, Nec, Nsk
1400 S San Gabriel Blvd, San Gabriel, CA 91776
4882 W 145 St, Hawthorne, CA 90250
Xin Wu
Managing
Aivya LLC
International Sourcing Service
550 Toyon Ave, San Jose, CA 95127
3031 Mattos Ave, San Jose, CA 95132
Xin Yu Wu
President
TRANS KINGDOM DEVELOPMENT CORP
8800 E Huntington Dr, San Gabriel, CA 91776
Xin Wu
Principal
Lumber Source
Ret Lumber/Building Materials
550 Toyon Ave, San Jose, CA 95127
Xin Wu
Principal, President
MANDALA CORP
Management Consulting Services · Nonclassifiable Establishments
625 Park Ave, South Pasadena, CA 91030
3016 E Colorado Blvd, Pasadena, CA 91107

Publications

Us Patents

Programmable Flux Gradient Apparatus For Co-Deposition Of Materials Onto A Substrate

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US Patent:
6364956, Apr 2, 2002
Filed:
Jan 26, 1999
Appl. No.:
09/237502
Inventors:
Youqi Wang - Atherton CA
Xin Di Wu - San Jose CA
Assignee:
Symyx Technologies, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
118726, 118723 EB, 392388, 21912115, 20429801
Abstract:
An apparatus for simultaneously depositing gradients components of two or more target materials onto a substrate is disclosed. The apparatus comprises a first target material source that directs a first target material towards the substrate and a second target material source that directs a second material towards the substrate. The apparatus further comprises a gradient shutter system that blocks a first predetermined amount of the first target material and a second predetermined amount of the second target material directed towards the substrate in order to generate gradients of the first and second target materials on the substrate. The gradients of the first and second target materials being simultaneously deposited onto the substrate to form a homogenous resulting material. A method for simultaneously depositing gradients of two or more target material onto a substrate is also disclosed.

Methods And Structures For Protecting Reticles From Esd Failure

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US Patent:
6376131, Apr 23, 2002
Filed:
Apr 4, 2000
Appl. No.:
09/542127
Inventors:
Jae Cho - Sunnyvale CA
Zhi-Min Ling - Cupertino CA
Xin X. Wu - Fremont CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G03F 900
US Classification:
430 5
Abstract:
A reticle that is modified to prevent bridging of the masking material (e. g. , chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

High Temperature Superconducting Josephson Junctions And Squids

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US Patent:
6476413, Nov 5, 2002
Filed:
Apr 24, 1998
Appl. No.:
09/446864
Inventors:
Quanxi Jia - Los Alamos NM
Xin Di Wu - San Jose CA
Steven R. Foltyn - Los Alamos NM
David W. Reagor - Los Alamos NM
Assignee:
The Regents of the University of California - Los Alamos NM
International Classification:
H01L 3922
US Classification:
257 33, 257 31, 257 34, 438 2
Abstract:
A high temperature superconducting Josephson junction device with ramp-edge geometry in which silver is combined in a composite with YBa Cu O , yttrium-barium-copper-oxide, to form the electrodes, or PrBa Cu O , praseodymium-barium-copper-oxide, to form the weak link.

Methods And Structures For Protecting Reticles From Electrostatic Damage

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US Patent:
6569584, May 27, 2003
Filed:
Jun 29, 2001
Appl. No.:
09/895538
Inventors:
Jonathan J. Ho - Fremont CA
Xin X. Wu - Fremont CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G03F 900
US Classification:
430 5
Abstract:
A reticle (mask) that is modified to prevent bridging of the masking material (e. g. , chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

Programmable Flux Gradient Apparatus For Co-Deposition Of Materials Onto A Substrate

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US Patent:
6632285, Oct 14, 2003
Filed:
Jul 30, 2001
Appl. No.:
09/919168
Inventors:
Youqi Wang - Atherton CA
Xin Di Wu - San Jose CA
Assignee:
Symyx Technologies, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
118726, 118723 EB
Abstract:
An apparatus for simultaneously depositing gradients components of two or more target materials onto a substrate is disclosed. The apparatus comprises a first target material source that directs a first target material towards the substrate and a second target material source that directs a second material towards the substrate. The apparatus further comprises a gradient shutter system that blocks a first predetermined amount of the first target material and a second predetermined amount of the second target material directed towards the substrate in order to generate gradients of the first and second target materials on the substrate. The gradients of the first and second target materials being simultaneously deposited onto the substrate to form a homogenous resulting material. A method for simultaneously depositing gradients of two or more target material onto a substrate is also disclosed.

Method Of Forming A Zener Diode

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US Patent:
6645802, Nov 11, 2003
Filed:
Jun 8, 2001
Appl. No.:
09/877690
Inventors:
Shahin Toutounchi - Pleasanton CA
Michael J. Hart - Palo Alto CA
Xin X. Wu - Fremont CA
Daniel Gitlin - Palo Alto CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 218234
US Classification:
438237, 438983, 438328
Abstract:
An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.

Method Of Generating An Ic Mask Using A Reduced Database

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US Patent:
6868537, Mar 15, 2005
Filed:
Feb 25, 2002
Appl. No.:
10/082991
Inventors:
Jonathan J. Ho - Fremont CA, US
Xin X. Wu - Fremont CA, US
Zicheng Gary Ling - San Jose CA, US
Jan L. de Jong - Cupertino CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
716 19, 716 20, 716 21
Abstract:
For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.

Semiconductor Die With High Density Offset-Inline Bond Arrangement

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US Patent:
7064450, Jun 20, 2006
Filed:
May 11, 2004
Appl. No.:
10/842756
Inventors:
Abu K. Eghan - San Jose CA, US
Richard C. Li - Cupertino CA, US
Xin X. Wu - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 23/48
US Classification:
257786, 257 48, 257692, 257773, 257775, 257780
Abstract:
A pad pattern of a die includes first and second sets of elongated pads. The first set of elongated pads is interleaved with the second set of elongated pads. Each of the elongated pads has a bond pad area and a probe pad. Each bond pad area has a first constant width along a substantial portion thereof. Similarly, each probe pad area has a second constant width along a substantial portion thereof. The first constant width is greater than the second constant width. Each elongated pad in the first set has a first orientation. Similarly, each elongated pad in the second set has a second orientation, opposite the first orientation.
Xin Wu from Dublin, CA, age ~47 Get Report