Wen Ching Wu

7727882, Jun 1, 2010

Dec 17, 2007

12/002780

Wen Wu - Milpitas CA, US
Chentao Yu - Sunnyvale CA, US
Girish Dixit - San Jose CA, US
Kenneth Jow - San Jose CA, US

Novellus Systems, Inc. - San Jose CA

H01L 21/4763

438627, 438625, 438643, 438656, 438675, 438685, 257E21584

A diffusion barrier film includes a layer of compositionally graded titanium nitride, having a nitrogen-rich portion and a nitrogen-poor portion. The nitrogen-rich portion has a composition of at least about 40% (atomic) N, and resides closer to the dielectric than the nitrogen-poor portion. The nitrogen-poor portion has a composition of less than about 30% (atomic) N (e. g. , between about 5-30% N) and resides in contact with the metal, e. g. , copper. The diffusion barrier film can also include a layer of titanium residing between the layer of dielectric and the layer of compositionally graded titanium nitride. The layer of titanium is often partially or completely converted to titanium oxide upon contact with a dielectric layer. The barrier film having a compositionally graded titanium nitride layer provides excellent diffusion barrier properties, exhibits good adhesion to copper, and reduces uncontrolled diffusion of titanium into interconnects.

8017523, Sep 13, 2011

May 16, 2008

12/122118

Hui-Jung Wu - Fremont CA, US
Daniel R. Juliano - Santa Clara CA, US
Wen Wu - San Jose CA, US
Girish Dixit - San Jose CA, US

Novellus Systems, Inc. - San Jose CA

H01L 21/4763

438687, 438627, 438675, 438678

Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embodiments, the methods involve depositing a copper seed bilayer on a barrier layer in a recessed feature on a partially fabricated semiconductor substrate. The bilayer has a copper alloy seed layer and a pure copper seed layer, with the pure copper seed layer is deposited on the copper alloy seed layer. The copper seed bilayers have reduced line resistance increase and better electromigration performance than conventional doped copper seed layers. Precise line resistance control is achieved by tuning the bilayer thickness to meet the desired electromigration performance.

8183553, May 22, 2012

Oct 29, 2009

12/608934

Prashant Phatak - San Jose CA, US
Tony Chiang - Campbell CA, US
Michael Miller - San Jose CA, US
Wen Wu - Pleasanton CA, US

Intermolecular, Inc. - San Jose CA

H01L 47/00

257 4, 257E45003, 365148

A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0. 1 and 1. 0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

8294219, Oct 23, 2012

Jul 24, 2008

12/179538

Sandra G. Malhotra - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sean Barstow - San Jose CA, US
Tony Chiang - Campbell CA, US
Prashant B. Phatak - San Jose CA, US
Wen Wu - Pleasanton CA, US
Sunil Shanker - Santa Clara CA, US

Intermolecular, Inc. - San Jose CA

H01L 21/02

257382, 257 68, 257296, 257 71, 257309, 257905, 257908, 257E27084, 257E27075, 257E27097, 257758, 257308

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

8298890, Oct 30, 2012

Sep 3, 2009

12/553918

Ronald John Kuse - Dublin CA, US
Monica Sawkar Mathur - San Jose CA, US
Wen Wu - Pleasanton CA, US

Intermolecular, Inc. - San Jose CA

H01L 21/336

438257, 438211, 438593, 438972, 257239, 257261, 257298, 257E21179, 257E21495

A semiconductor memory element is described, including a substrate including a source region, a drain region, and a channel region, a tunnel oxide over the channel region of the substrate, a charge storage layer over the tunnel oxide, a charge blocking layer over the charge storage layer, and a control gate over the charge blocking layer. The charge blocking layer further includes a first layer including a transition metal oxide, a second layer including a metal silicate, a third layer including the transition metal oxide of the first layer.

8318573, Nov 27, 2012

Dec 27, 2011

13/337611

Sandra G. Malhotra - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sean Barstow - San Jose CA, US
Tony Chiang - Campbell CA, US
Prashant B. Phatak - San Jose CA, US
Wen Wu - Pleasanton CA, US
Sunil Shanker - Santa Clara CA, US

Intermolecular, Inc. - San Jose CA

H01L 21/02

438382, 257E21004, 257E27084, 257E27075, 257E27097, 257 68, 257296

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

8502187, Aug 6, 2013

Apr 24, 2012

13/454392

Prashant Phatak - San Jose CA, US
Tony Chiang - Campbell CA, US
Michael Miller - San Jose CA, US
Wen Wu - Pleasanton CA, US

Intermolecular, Inc. - San Jose CA

H01L 47/00

257 4, 257E45003

A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0. 1 and 1. 0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

8592282, Nov 26, 2013

Oct 19, 2012

13/656585

Sean Barstow - San Jose CA, US
Tony P. Chiang - Campbell CA, US
Pragati Kumar - Santa Clara CA, US
Prashant B. Phatak - San Jose CA, US
Sunil Shanker - Santa Clara CA, US
Wen Wu - Pleasanton CA, US

Intermolecular, Inc. - San Jose CA

H01L 21/02

438382, 257E21004, 257E27084, 257E27075, 257E27097, 257 68, 257296

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.