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Wen Jye Huang

from State College, PA
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Also known as:
Wen J Huang, Wenjye Huang, Wenjye Jye Huang, Wenjye Jye Huangwen
Related to:
Xiangdong Huang
Connected to:
Agnes S Huang, 63Ailin Huang, 36Aizhu Huang, 60Alexandra Y Huang, 30Amanda Huang, 35An F Huang, 54Anderson Huang, 29Anna K Huang, 52Anne Huang, 35Annie A Huang, 73

Wen Huang Phones & Addresses

  • State College, PA
  • San Jose, CA
  • Athens, OH

Education

School / High School: Columbia University School of Law

Ranks

Licence: New York - Currently registered Date: 2005

Professional Records

Lawyers & Attorneys

Wen Huang Photo 1

Wen Huang - Lawyer

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Address:
King & Wood Mallesons
(344) 383-09xx (Office)
Licenses:
New York - Currently registered 2005
Education:
Columbia University School of Law
Specialties:
Real Estate - 34%
Mergers / Acquisitions - 33%
Corporate / Incorporation - 33%

License Records

Wen Hui Huang

License #:
33577 - Active
Issued Date:
Jun 30, 2015
Renew Date:
Dec 1, 2015
Expiration Date:
Nov 30, 2017
Type:
Certified Public Accountant

Wen Hua Huang

License #:
04849 - Active
Category:
Accountants
Issued Date:
Mar 23, 2009
Expiration Date:
Jun 30, 2018
Type:
Certified Public Accountant

Business Records

Name / Title
Company / Classification
Phones & Addresses
Wen Tai Huang
President
Fat Turtle Digital, Inc
197 Anaheim Ter, Sunnyvale, CA 94086
Wen Hua Huang
President
PC PORTABLE MANUFACTURER, INC
11701 Southshore Ct, Cupertino, CA 95014
2025 Terra Ln, Arcadia, CA 91007
Wen Yuan Huang
S-Pet, A California Limited Partnership
Ret Misc Merchandise
201 San Antonio Cir, Mountain View, CA 94040
Wen Yuan Huang
President
STARCON CORPORATION
5 3 St #430, San Francisco, CA 94103
1671 The Alameda, San Jose, CA 95126
170 Columbus Ave, San Francisco, CA 94133
(916) 941-9844
Wen Heng Huang
CHH INTERNATIONAL, LLC
Business Services at Non-Commercial Site · Nonclassifiable Establishments
1527 W State Hwy 114 STE 500-198, Grapevine, TX 76051
606 Cold Bay Ln, Euless, TX 76039
1733 Chesterton Cir, San Jose, CA 95133
Wen Xiang Huang
HIBACHI HOUSE BUFFET INC
Wen Yuan Huang
President
S52, INC
PO Box 60501, Palo Alto, CA 94306
Wen Yuan Huang
President
WYH 1671 INVESTMENTS, INC
318 S Grant St #4A, San Mateo, CA 94401

Publications

Us Patents

System For Modeling A Processor-Encoder Interface By Counting Number Of Fast Clock Cycles Occuring In One Slower Clock Cycle And Triggering A Domain Module If Fast Clock Reaches The Corresponding Number Of Cycles

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US Patent:
6513126, Jan 28, 2003
Filed:
Jan 6, 2000
Appl. No.:
09/477692
Inventors:
Wen Huang - Sunnyvale CA
Scarlett Wu - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 104
US Classification:
713500, 713501, 713502, 713503, 713600
Abstract:
An interface is provided between a digital signal processor or the like and an output encoder or the like that is capable of counting a system clock of the digital signal processor, generally having a higher clock rate, with respect to at least one or more clocks generally having a lower clock rate. The digital signal processor system clock is passed to the interface that has at least one or more counters. When the accumulation of the system clock reaches a corresponding number of the other clocks, a domain module in the output encoder is triggered, and the corresponding clock counters are reset. The interface may be implemented as a software modeling routine suitable for utilization by a digital signal processor simulator to facilitate complete whole cycle simulation in which multiple clocks having various clock rates may be simulated and compared with a behavior reference. The interface provides cycle-by-cycle comparison of the clocks in an asynchronous domain. The output encoder may be compliant with an International Elector-technical Commission standard such as an audio encoder standard.

Method And Apparatus To Use Non-Volatile Read/Write Memory For Bootstrap Code And Processes

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US Patent:
6604195, Aug 5, 2003
Filed:
Jun 28, 2000
Appl. No.:
09/606968
Inventors:
Jainendra Kumar - Fremont CA
Joseph C. Harrow - San Ramon CA
Lucy Chiu - Fremont CA
Sami Khan - Fremont CA
Wen Huang - Cupertino CA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 9445
US Classification:
713 2
Abstract:
A reset pin of a non-volatile read/write memory, which stores boot code, is provided with a reset signal in response to a system reset output by a watchdog timer or other external circuitry. The reset signal causes the non-volatile read/write memory to be placed into read mode. Accordingly, even when a system reset occurs while the non-volatile read/write memory is in write mode, a hang state can be avoided since the memory will be reset to read mode before attempting to read boot code for a reboot operation.

Method And Apparatus For Connecting Two-Wire Serial Interface And Single-Wire Serial Interface With High Transmission Speed

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US Patent:
6735657, May 11, 2004
Filed:
Jun 30, 2000
Appl. No.:
09/608420
Inventors:
Peter Falk - Sunnyvale CA
Joseph C. Harrow - San Ramon CA
Wen Huang - Cupertino CA
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 1314
US Classification:
710305, 710310
Abstract:
A two-wire interface having a receive wire and a transmit wire is coupled for communication with a single-wire serial interface to provide for relatively high-speed data transmission. In one aspect, controllable buffers are coupled to the transmit and receive lines of the two-wire serial interface. The outputs from the two buffers are coupled to a commnon line which is also coupled to the single line of the single-wire interface. The transmit buffer and/or read buffer and/or transmission from the single-wire interface are controlled, e. g. , such as using control signals provided by software, such that the transmit buffer from the two-wire interface is enabled only when transmission from the single-wire interface is disabled and transmission from the single-wire interface is permitted only when the transmit buffer of the two-wire interface is disabled. By this type of system, it is possible to avoid coupling which involves a pull-up transistor and the like, avoiding lengthening the rise time or fall time of signals and providing the potential for relatively high data transmission rates such as 1 Mbps or more.

Method For Independent Dynamic Range Control

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US Patent:
6782366, Aug 24, 2004
Filed:
May 15, 2000
Appl. No.:
09/571691
Inventors:
Wen Huang - Sunnyvale CA
Winnie K. W. Lau - San Jose CA
Brendan J. Mullane - Tokyo, JP
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G10L 1900
US Classification:
704500, 704501, 704224, 704230
Abstract:
Different dynamic range control values are applied to the 2-channel and m-channel outputs without repeating the inverse transform of the audio samples. First, m-channel dynamic range control values are applied to audio samples in the frequency domain (âfrequency samplesâ or âfrequency coefficientsâ). The frequency samples are then inverse transformed to generate audio samples in the time domain (âtime samplesâ). The time samples are duplicated to two sets where the 2-channel dynamic range control values are applied to one set of time samples. 2-channel dynamic range control values include 2-channel final scales that, when multiplied with the first set of time samples, at least partially remove the effects of the m-channel dynamic range control and readjust the dynamic range for 2-channel output. The first set and the second set are then windowed. Thus, independent dynamic range control for the m-channel output and the 2-channel output are achieved without repeating the inverse transform, which is computational and/or memory intensive.

Method For Independent Dynamic Range Control

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US Patent:
6785655, Aug 31, 2004
Filed:
May 15, 2000
Appl. No.:
09/571399
Inventors:
Wen Huang - Sunnyvale CA
Winnie K. W. Lau - San Jose CA
Brendan J. Mullane - Tokyo, JP
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G10L 1900
US Classification:
704500, 704501, 704224, 704230
Abstract:
Different dynamic range control values are applied to the 2-channel and m-channel outputs without repeating the inverse transform or the windowing of the audio samples. First, m-channel dynamic range control values are applied to audio samples in the frequency domain (âfrequency samplesâ or âfrequency coefficientsâ). The frequency samples are then inverse transformed to generate audio samples in the time domain (âtime samplesâ) and windowed to generate windowed time samples. The windowed time samples are saved and the 2-channel dynamic range control values are applied to the windowed time samples. 2-channel dynamic range control values include 2-channel scale factors that, when multiplied with groups of the windowed time samples, at least partially remove the effects of windowing and the m-ch dynamic range control values applied in the frequency domain and readjust the dynamic range for 2-channel output. Thus, a set of windowed time samples under m-channel dynamic range control values and a set of windowed time samples under 2-channel dynamic range control values are generated without repeating the inverse transform or the windowing, which are computational and/or memory intensive.

Time Division Multiplexing Method And Apparatus For Asynchronous Data Stream

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US Patent:
6876678, Apr 5, 2005
Filed:
Feb 4, 1999
Appl. No.:
09/244361
Inventors:
Steven Chow - San Carlos CA, US
Jicheng Ye - Cupertino CA, US
Wen Huang - Cupertino CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H04J003/02
H04L012/66
US Classification:
370538, 370463, 370493
Abstract:
A Serial Communications Controller (SCC) is configured to provide TDM multiplexing of signals regardless of whether such signals are synchronous or asynchronous signals. When an asynchronous signal is detected, the data rate of the asynchronous signal is automatically measured. The two data streams are buffered, e. g. , by FIFOs. Data is clocked-out from the FIFOs into periods of a TDM signal which has a period at least twice that of the faster of the two input signals. In one embodiment alternate periods of the TDM signal are used for the first and second input signals. Bits from the slower of the two input signals are repeated a sufficient number of times, in the TDM signal, that ratio of the rate at which new data bits from the second signal are placed into the TDM signal, to the rate of output of bits from the first stream onto the TDM signal equals (on average) the ratio of the data rates of the first and second input streams. When the ratio of the data rates of the input streams is non-integral, the number of times the bits from the second or slower data stream are repeated, is dithered to keep accumulated skew of data rates in the TDM signal less than a predetermined threshold, such as the duration of a TDM period.

Method And System For Programmable Field Statistic For Picture Cyclic Redundancy Check (Crc)

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US Patent:
7149954, Dec 12, 2006
Filed:
Aug 25, 2003
Appl. No.:
10/646717
Inventors:
Darren Neuman - Palo Alto CA, US
Chengfuh Jeffrey Tang - Saratoga CA, US
Yao-Hua Steven Tseng - Fremont CA, US
Guang Ting Shih - San Jose CA, US
Wen Huang - San Jose CA, US
Charles Thomas Monahan - Mountain View CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 13/09
H04N 7/64
US Classification:
714807, 348180, 348192
Abstract:
Provided is a system and method for performing CRC analysis in a video test bench. An exemplary system includes a memory configured for storing a required number representative of the data fields to be analyzed. A module is coupled at least indirectly to the memory and configured for (i) receiving an input data stream, (ii) performing cyclic redundancy check (CRC) analysis of the received data stream, and (iii) producing an output representative of an actual number of received data fields analyzed. The input data stream includes synchronization markers defining boundaries of each of the received data fields. Next, a comparator is configured for (i) comparing the required number and the actual number and (ii) producing a disabling signal when the actual number matches the required number. A detector is coupled to the comparator and configured for (i) receiving the input data stream and sensing a presence of the synchronization markers, (ii) receiving the disabling signal, and (iii) disabling the CRC module when the disabling signal is received.

System And Method For Determining Video Subcarrier Phase

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US Patent:
7425991, Sep 16, 2008
Filed:
Aug 8, 2005
Appl. No.:
11/200343
Inventors:
Wen Huang - San Jose CA, US
Brad Delanghe - Sunnyvale CA, US
Aleksandr Movshovich - Santa Clara CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04N 9/45
H04N 17/02
US Classification:
348505, 348194
Abstract:
A system and method for determining phase of a subcarrier (e. g. , a jittering video subcarrier). Various aspects of the present invention may comprise determining at least one weighting factor based, at least in part, on a subcarrier synchronization signal (e. g. , a video synchronization signal). A first subcarrier phase sample and at least a second subcarrier phase sample may then be obtained. Subcarrier phase may then be determined by interpolating between the first subcarrier phase sample and the second subcarrier phase sample, where such interpolation (e. g. , linear interpolation) may be based, at least in part, on the determined weighting factor(s).
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Wen Jye Huang from State College, PA Get Report