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Wei C Xia

from El Monte, CA
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Related to:
Son H Tu, 57Simon K TuSandy Y Pu, 69Quyen Dat Tu, 51Van Q Tu, 53Jenny Tu, 65Tu Tiger, 51Diane Tu, 35Tu D Binh
Connected to:
Al P Xia, 60Angela Z Xia, 41Chunliang Xia, 61Cindy Xia, 29Frank K Xia, 36Ganyuan G Xia, 57Gary Xia, 34Haifeng Xia, 44Haiying Xia, 38Haoran Xia, 33

Wei Xia Phones & Addresses

  • El Monte, CA

Resumes

Resumes

Wei Xia Photo 1

Wei Xia

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Position:
Supply Chain Management at Clipper Windpower
Location:
Greater Los Angeles Area
Industry:
Renewables & Environment
Work:
Clipper Windpower since Sep 2009
Supply Chain Management
GPS Capital Markets Jun 2009 - Aug 2009
Summer Analyst
Veeco Instruments Jul 2006 - Feb 2009
Applications Scientist
Merck & Co. May 2005 - Jul 2006
Senior Research Scientist
Education:
Pepperdine University, The George L. Graziadio School of Business and Management 2007 - 2009
MBA, Finance● Association for Corporate Growth Business Valuation Competition Finalist, Southern California Cup 2009 ● E2B 2008: Design of Retail Marketing Strategy • Designed a retail marketing strategy for an European orthopedics bracing & support business to enter the North America retail market • Developed product positioning and pricing strategy through aggressive field marketing research and competitive analysis • Performed financial analysis and projection to propose marketing budget and program implementation roadmap • Marketing plan was praised by company executives for originality and for consistence with the company’s strategic objectives University of Arizona 2000 - 2005
Ph.D, Chemistry● Characterization of organic electronic molecular materials ● Critical interface study in organic FET and PV devices ● Strong analytical skills in XRD, SPM, and Spectroscopy. ● Student mentoring and multiuser facility management Dalian University of Technology 1995 - 1999
B.S., Polymer Science and Engineering• Reporter, DUT campus radio
Skills:
Technology & Applications Development
Business Development & Client Relationship Management
Interests:
Business Valuation & Corporate Finance, Renewable Energy, Argentine Tango
Honor & Awards:
● Award of Excellence, Merck & Co. 2005, ● Carl S. Marvel Fellowship, U of Arizona, 2004, ● Pfizer Research Fellowship, 2004
Wei Xia Photo 2

Smith College

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Location:
Northampton, Massachusetts
Industry:
Financial Services
Work:
Deutsche Bank Securities - New York, NY Jun 2012 - Aug 2012
Investment Banking Summer Analyst
Smith College Investment Club - Northampton, MA Sep 2010 - May 2012
Sector Head (Consumer & Retail)
PwC Consulting - Shanghai May 2011 - Aug 2011
Summer Intern
John Leggott Student Orchestra - United Kingdom Sep 2008 - May 2009
Second Violinist
Education:
Smith College 2010 - 2013
BA, Mathematics, Economics
Skills:
Microsoft Office
Pitch Books
Violin
Mathematical Analysis
Programming (Java, VB, SQL)
Financial Modeling
Languages:
English
Chinese
Japanese
Wei Xia Photo 3

Wei Xia

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Wei Xia Photo 4

Wei Xia

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Wei Xia Photo 5

Wei Xia

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Wei Xia Photo 6

Sr Principal Scientist At Broadcom

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Location:
Greater Los Angeles Area
Industry:
Semiconductors
Wei Xia Photo 7

Wei Xia Granite Bay, CA

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Work:
HCM, Financial, CRM, Campus Solution

1995 to 2000
Peoplesoft consultant
Peoplesoft consultantTexas
Jul 2013 to Mar 2014
HCM, Financial, CRM, Campus Solution

Oct 2012 to 2013
Peoplesoft Consultant
HCM, Financial, CRM, Campus Solution

2012 to 2013
PeopleSoft Consultant
HCM, Financial, CRM, Campus Solution

2012 to 2012
University of Texas at Arlington
Arlington, TX
2012 to 2012
Verizon
Folsom, CA
2011 to 2011
Campus Solutions

2010 to 2011
Student attributes
Government of South Australia

2008 to 2010
University of South Australia

2008 to 2008
Griffith University HCM and Campus Solutions

2007 to 2008
Job Data admin
Oracle University
San Francisco, CA
2007 to 2007
San Francisco State University
San Francisco, CA
2007 to 2007
Lab Safety Supply
Janesville, WI
2005 to 2005
Peoplesoft Inc
Pleasanton, CA
2004 to 2005
Sales and Marketing
IBM China
DongFeng, CN
2003 to 2003
Cognex
Boston, MA
2003 to 2003
Packing Slip

2002 to 2003
Rain Bird
Glendora, CA
2002 to 2002
Intersil
Palm Bay, FL
2002 to 2002
Medibank, Australia

2002 to 2002
Vitria Technology
Sunnyvale, CA
2002 to 2002
Peoplesoft Financial

2001 to 2001
CKE
Anaheim, CA
1999 to 2001
Carls Jr
PeopleSoft, Inc
Los Angeles, CA
1996 to 2001
Sr. Professional Service Consultant
Verio
Dallas, TX
2000 to 2000
Order Management implementation
Serta Mattress
Vacaville, CA
2000 to 2000
Order management
Micron technology
Boise, ID
1999 to 1999
Order Management implementation
Headway Technologies
Milpitas, CA
1999 to 1999
NEC
Santa Clara, CA
1999 to 1999
Supply-Chain Management implementation
3Com
Santa Clara, CA
1998 to 1998
Sun Microsystems
Milpitas, CA
1998 to 1998
Samsung SDD
Seoul, KR
1997 to 1997
Bausch & Lomb
Rochester, NY
1997 to 1997
Western Digital
Irvine, CA
1996 to 1996
Red Pepper/Peoplesoft Manufacturing

1995 to 1996
Coors filler
Red Pepper Software Company

1995 to 1996
Sr. application engineer
TRW Financial Systems, Inc

1993 to 1995
Lead software engineer
Litton/IA Corporation

1991 to 1993
Sr. Software Engineer
Software Engineer
1990 to 1991
Education:
SUNY at Albany
Albany, NY
1987
M.S. in Computer Science

Business Records

Name / Title
Company / Classification
Phones & Addresses
Wei Xia
President
VIVIX CORPORATION
Nonclassifiable Establishments
663 Brea Cyn Rd #5, Walnut, CA 91789
5656 Rosemead Blvd, Temple City, CA 91780
454 Golden Spg Dr, Pomona, CA 91765
(909) 895-7560
Wei Yi Xia
President
GARFIELD VENTURE INCORPORATION
2652 Lee Ave, South El Monte, CA 91733

Publications

Us Patents

Method For Forming A One-Time Programmable Metal Fuse And Related Structure

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US Patent:
8178944, May 15, 2012
Filed:
Jun 22, 2009
Appl. No.:
12/456833
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Akira Ito - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/00
US Classification:
257529, 257209, 257E23149
Abstract:
According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

Method For Fabricating A Mos Transistor With Reduced Channel Length Variation And Related Structure

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US Patent:
8269275, Sep 18, 2012
Filed:
Oct 21, 2009
Appl. No.:
12/589357
Inventors:
Xiangdong Chen - Irvine CA, US
Wei Xia - Irvine CA, US
Henry Kuo-Shun Chen - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/78
US Classification:
257336, 257343, 257344, 257E29256, 438286, 438201, 438202
Abstract:
According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

Programmable Fuse

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US Patent:
8455977, Jun 4, 2013
Filed:
May 8, 2012
Appl. No.:
13/466986
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Akira Ito - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/00
US Classification:
257529, 257209, 257E23149
Abstract:
According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

Method For Fabricating A Decoupling Composite Capacitor In A Wafer And Related Structure

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US Patent:
8497564, Jul 30, 2013
Filed:
Aug 13, 2009
Appl. No.:
12/583016
Inventors:
Xiangdong Chen - Irvine CA, US
Wei Xia - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/92
H01L 21/02
US Classification:
257532
Abstract:
According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.

Zener Diode Structure And Process

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US Patent:
8502320, Aug 6, 2013
Filed:
Sep 30, 2011
Appl. No.:
13/250563
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 21/70
US Classification:
257368, 257E21632, 438200
Abstract:
A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non-junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Method For Fabricating A Flash Memory Cell Utilizing A High-K Metal Gate Process And Related Structure

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US Patent:
8558300, Oct 15, 2013
Filed:
Nov 6, 2009
Appl. No.:
12/590370
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Frank Hui - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/788
US Classification:
257316, 257412
Abstract:
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

Finfet Based One-Time Programmable Device And Related Method

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US Patent:
8570811, Oct 29, 2013
Filed:
Aug 26, 2011
Appl. No.:
13/219414
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 11/34
US Classification:
36518524, 36518514, 36518528, 36518521
Abstract:
According to one embodiment, a one-time programmable (OTP) device comprises a memory FinFET in parallel with a sensing FinFET. The memory FinFET and the sensing FinFET share a common source region, a common drain region, and a common channel region. The memory FinFET is programmed by having a ruptured gate dielectric, resulting in the sensing FinFET having an altered threshold voltage and an altered drain current. A method for utilizing such an OTP device comprises applying a programming voltage for rupturing the gate dielectric of the memory FinFET thereby achieving a programmed state of the memory FinFET, and detecting by the sensing FinFET the altered threshold voltage and the altered drain current due to the programmed state of the memory FinFET.

Method For Fabricating A Mim Capacitor Using Gate Metal For Electrode And Related Structure

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US Patent:
8614497, Dec 24, 2013
Filed:
Aug 7, 2009
Appl. No.:
12/462692
Inventors:
Wei Xia - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Akira Ito - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 29/92
US Classification:
257532, 257E29343
Abstract:
According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.
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Wei C Xia from El Monte, CA Get Report