Wah Wong Phones & Addresses
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5518 Santa Anita Ave, Arcadia, CA 91006 (626) 401-9018
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Los Angeles, CA
Business Records
Name / Title
Company / Classification
Phones & Addresses
Managing Broker
ANK Properties
A C T Mercantile Corp
Chemicals
A C T Mercantile Corp
Chemicals
213 938 Howe, Vancouver, BC V6Z 1N9
(604) 682-1992
(604) 682-1992
CHINA CITY LLC
President
DISCLINK, INC
Nonclassifiable Establishments
Nonclassifiable Establishments
16725 E Gale Ave, Hacienda Heights, CA 91745
16725 Gale Ave, Whittier, CA 91745
16725 Gale Ave, Whittier, CA 91745
Publications
Isbn (Books And Publications)
Protecting Children, Protecting the Future: The Story of UNICEF in Bangladesh
View page
Author
Wah Wong
ISBN #
9280631845
Us Patents
Method For Fabricating A Non-Planar Nitride-Based Heterostructure Field Effect Transistor
View pageUS Patent:
6830945, Dec 14, 2004
Filed:
Mar 12, 2003
Appl. No.:
10/386960
Inventors:
Jeong Sun Moon - Chatsworth CA
Paul Hashimoto - Los Angeles CA
Wah S. Wong - Montebello CA
David E. Grider - Charlotte NC
Paul Hashimoto - Los Angeles CA
Wah S. Wong - Montebello CA
David E. Grider - Charlotte NC
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 2100
US Classification:
438 22, 438 94
Abstract:
A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
Non-Planar Nitride-Based Heterostructure Field Effect Transistor
View pageUS Patent:
7247893, Jul 24, 2007
Filed:
Sep 1, 2004
Appl. No.:
10/932811
Inventors:
Jeong Sun Moon - Chatsworth CA, US
Paul Hashimoto - Los Angeles CA, US
Wah S. Wong - Montebello CA, US
David E. Grider - Charlotte NC, US
Paul Hashimoto - Los Angeles CA, US
Wah S. Wong - Montebello CA, US
David E. Grider - Charlotte NC, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 29/20
US Classification:
257200, 257194, 257201, 257E29249, 438167, 438172
Abstract:
A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
Piezoelectric Mems Integration With Gan Technology
View pageUS Patent:
7514759, Apr 7, 2009
Filed:
Apr 11, 2005
Appl. No.:
11/104395
Inventors:
Sarabjit Mehta - Calabasas CA, US
David E. Grider - Charlotte NC, US
Wah S. Wong - Montebello CA, US
David E. Grider - Charlotte NC, US
Wah S. Wong - Montebello CA, US
Assignee:
HRL Laboratories, LLC - Malibu CA
International Classification:
H01L 29/84
H01L 21/00
H01L 21/00
US Classification:
257416, 438 55
Abstract:
A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.
Ga/A1Gan Heterostructure Field Effect Transistor With Dielectric Recessed Gate
View pageUS Patent:
20040021152, Feb 5, 2004
Filed:
Aug 5, 2002
Appl. No.:
10/214422
Inventors:
Chanh Nguyen - Calabasas CA, US
Jeong-Sun Moon - Chatsworth CA, US
Wah Wong - Montebello CA, US
Miro Micovic - Newbury Park CA, US
Paul Hashimoto - Los Angeles CA, US
Jeong-Sun Moon - Chatsworth CA, US
Wah Wong - Montebello CA, US
Miro Micovic - Newbury Park CA, US
Paul Hashimoto - Los Angeles CA, US
International Classification:
H01L031/0328
US Classification:
257/192000
Abstract:
The present invention utilizes the strong piezoelectric effect, found in group-III nitride materials to circumvent the need to selectively remove Gallium Nitride (GaN) in the fabrication of GaN/AlGaN Heterostructure Field Effect Transistors. The transistor is comprised of a semi-insulating substrate a buffer layer which is in continual contact with the semi-insulating substrate A GaN active channel is atop the buffer layer An AlGaN barrier in laid on top of, and is in continual contact with, the GaN active channel Thereafter, there is a source contact and a drain contact both in physical contact with the GaN active channel There is a gate upon the AlGaN barrier and between the source contact and a drain contact At least one dielectric stressor is placed upon the AlGaN barrier The dielectric stressors are between the gate and the source and drain contacts.
Two-Terminal Semiconductor Diode Arrangement
View pageUS Patent:
48004200, Jan 24, 1989
Filed:
May 14, 1987
Appl. No.:
7/049875
Inventors:
James C. Chen - Torrance CA
Wah S. Wong - Montebello CA
Cheng K. Pao - Torrance CA
Wah S. Wong - Montebello CA
Cheng K. Pao - Torrance CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2336
H01L 2314
H01L 2184
H01L 2314
H01L 2184
US Classification:
357 76
Abstract:
A two-terminal semiconductor diode device and method for manufacturing the same is disclosed. The semiconductor diode geometry is defined by mesa etching. An ohmic contact is disposed on the flat topped summit of the mesa and another ohmic contact in the shape of a ring is disposed on the bottom layer of the diode. A dielectric layer disposed over the diode has a via hole therethrough to make external contact to a metallic heat sink and ground. A substrate layer supports the semiconductor diode and has a second offset via hole therethrough to the ring contact for external circuit contact and biasing of the diode. The offset via hole simplifies the manufacturing process. Additionally, the active area of the diode makes direct contact to the heat sink improving heat transfer from the device.
Beam Lead Mixer Diode
View pageUS Patent:
48557960, Aug 8, 1989
Filed:
Jun 6, 1986
Appl. No.:
6/871236
Inventors:
Wah S. Wong - Montebello CA
Cheng P. Wen - Mission Viejo CA
Jen K. Kung - Rolling Hills CA
Cheng P. Wen - Mission Viejo CA
Jen K. Kung - Rolling Hills CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2948
H01L 2348
H01L 2702
H01L 2348
H01L 2702
US Classification:
357 15
Abstract:
A beam lead diode configuration is described, employing a planar proton bombarded conversion region and a low-permittivity dielectric separator. The diode enjoys the mechanical ruggedness of the conventional planar diodes and the electrical performance of conventional mesa-type diodes. The diode structure results in the absence of N-type mesa structures on the substrate, allowing fabrication by relatively low-cost, high-yield photolithographic processes.
Plated Nickel-Gold/Dielectric Interface For Passivated Mmics
View pageUS Patent:
58613412, Jan 19, 1999
Filed:
Jul 15, 1996
Appl. No.:
8/680453
Inventors:
Cheng P. Wen - Mission Viego CA
Wah S. Wong - Montebello CA
Arlene E. Arthur - Torrance CA
Wah S. Wong - Montebello CA
Arlene E. Arthur - Torrance CA
Assignee:
Raytheon Company - El Segundo CA
International Classification:
H01L 21441
US Classification:
438628
Abstract:
A thin film (at least one atomic layer to about 400. ANG. ) of nickel is electrolytically plated on top of electrolytically-plated gold electrodes in GaAs monolithic microwave integrated circuits (MMICs) without any additional photoresist masking step. The thin electrolytically-plated nickel film improves adhesion of a passivating dielectric layer (e. g. , silicon dioxide, silicon nitride, and silicon oxynitride) formed on the electrolytically-plated gold electrodes. The electrolytically-plated nickel film can be removed locally to facilitate the fabrication of plated silver bumps (for off-chip electrical connections and thermal paths) on passivated flip chip MMICs.
High Power Prematched Mmic Transistor With Improved Ground Potential Continuity
View pageUS Patent:
59988177, Dec 7, 1999
Filed:
Nov 3, 1997
Appl. No.:
8/963529
Inventors:
Cheng P. Wen - Viejo CA
Peter Chu - Hawthorne CA
Michael R. Cole - Los Angeles CA
Wah S. Wong - Montebello CA
Robert F. Wang - Torrance CA
Liping D. Hou - Palo Verdes CA
Peter Chu - Hawthorne CA
Michael R. Cole - Los Angeles CA
Wah S. Wong - Montebello CA
Robert F. Wang - Torrance CA
Liping D. Hou - Palo Verdes CA
Assignee:
Raytheon Company - Lexington MA
International Classification:
H01L 2980
US Classification:
257259
Abstract:
A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.