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Vinh Xuong Lam

from Hayward, CA
Age ~63
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Also known as:
Vinh X Lam, Binh Lam
Phone and address:
929 Neil Way, Hayward, CA 94545
(510) 846-6677
Related to:
Hong X Lam, 73Hung X Lam, 71Uy L Lam, 38Anh H Lam, 62Thanh V Lam, 35Kinh LylamPhuanh Lam, 55Toan X Lam, 69Vanessa Lam, 65Binh L Lam, 38
Connected to:
Abdoulaye Lam, 42Adeline Lam, 46Alisa L Lam, 65Amethyst Lam, 56Angelica M Lam, 57Anna M Lam, 68Awilda O Lam, 54Beatrice M Lam, 76Belle B Lam, 76Blaine C Lam, 31

Vinh Lam Phones & Addresses

  • 929 Neil Way, Hayward, CA 94545 (510) 846-6677
  • 1151 75Th Ave, Oakland, CA 94621 (510) 878-2399
  • 5415 Cole St, Oakland, CA 94601 (510) 533-6596

Professional Records

Medicine Doctors

Vinh Lam Photo 1

Vinh D. Lam

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Specialties:
Family Medicine, Urgent Care Medicine
Work:
Houston Urgent Care
13977 Westheimer Rd STE D, Houston, TX 77077
(281) 558-4300 (phone), (281) 558-4303 (fax)
Education:
Medical School
St. George's University School of Medicine, St. George's, Greneda
Graduated: 2004
Procedures:
Continuous EKG
Vaccine Administration
Conditions:
Abnormal Vaginal Bleeding
Acne
Acute Bronchitis
Acute Conjunctivitis
Acute Upper Respiratory Tract Infections
Languages:
English
Spanish
Vietnamese
Description:
Dr. Lam graduated from the St. George's University School of Medicine, St. George's, Greneda in 2004. He works in Houston, TX and specializes in Family Medicine and Urgent Care Medicine.
Vinh Lam Photo 2

Vinh T. Lam

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Specialties:
Pediatric Surgery
Work:
St Joseph Heritage Medical GroupPediatric Surgical Associates
1120 W Ln Veta Ave STE 100, Orange, CA 92868
(714) 361-4480 (phone), (714) 361-4490 (fax)
Education:
Medical School
Harvard Medical School
Graduated: 1991
Conditions:
Appendicitis
Languages:
English
Spanish
Description:
Dr. Lam graduated from the Harvard Medical School in 1991. He works in Orange, CA and specializes in Pediatric Surgery. Dr. Lam is affiliated with Anaheim Regional Medical Center, CHOC Childrens At Mission Hospital, CHOC Childrens Hospital and Fountain Valley Regional Hospital & Medical Center.

Resumes

Resumes

Vinh Lam Photo 3

Vinh Lam

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Position:
Instructional Material Reviewer at California Department of Education, Vice Principal at Fremont Unified School District
Location:
San Francisco Bay Area
Industry:
Education Management
Work:
California Department of Education since Jun 2013
Instructional Material Reviewer
Fremont Unified School District since Jul 2007
Vice Principal
Fremont Unified School District - Fremont, CA Aug 2006 - Jun 2007
Assistant Principal
Alameda City Unified School District Aug 2004 - Jun 2006
Vice Principal
Hayward Unified School District - Hayward, Ca Aug 2001 - Jun 2004
Assistant Principal
Education:
CSU Hayward 1998 - 2001
M.Ed, Education Administration CSU Sacramento 1995 - 1997
T.Ed, Teacher Education UC Davis 1990 - 1995
B.A., Mathematics
Skills:
Technology Implementation
Mathematics Education
Secondary Education
Instructional Technology
Technology Integration
Staff Development
Educational Technology
ESL
Interests:
Outdoor activities, gadgets and technology, a good book.
Vinh Lam Photo 4

Vinh Lam

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Location:
United States
Vinh Lam Photo 5

Installation Operations Manager At Sunbelt Controls

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Location:
San Francisco Bay Area
Industry:
Construction
Vinh Lam Photo 6

Post-Doctoral Scholar At California Institute Of Technology

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Location:
Pasadena, California
Industry:
Research
Work:
California Institute of Technology - Pasadena, CA Jan 2007 - Aug 2011
Post-doctoral Scholar; Dr. Shu-ou Shan Laboratory
University of Illinois at Chicago Jun 2003 - Dec 2006
Graduate Student with Dr. Leslie W.-M. Fung
Loyola University Chicago 2000 - 2003
Graduate Student with Dr. Leslie W.-M. Fung
San Francisco State University 1996 - 2000
Undergraduate Researcher with Dr. Clifford E. Berkman
San Francisco VA Medical Center Jun 1999 - Sep 1999
Summer undergraduate researcher with Dr. Andrew Maudsley
Education:
University of Illinois at Chicago 2003 - 2006
Ph.D, Biochemistry San Francisco State University 1996 - 2000
BS, Chemistry
Vinh Lam Photo 7

Sr. Cmp Process Engineer At Headway Technologies

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Position:
Sr. CMP Process Development Engineer at Magic Technologies
Location:
Milpitas, California
Industry:
Semiconductors
Work:
Magic Technologies since Mar 2011
Sr. CMP Process Development Engineer

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vinh Lam
Assistant Principal
Fremont Unified School District
Elementary/Secondary School
38442 Fremont Blvd, Fremont, CA 94536
(510) 505-7300
Vinh Xuong Lam
Managing
Fortune Trade LLC
Investment Business · Whol Nondurable Goods
5415 Cole St, Oakland, CA 94601

Publications

Us Patents

Method To Connect A Magnetic Device To A Cmos Transistor

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US Patent:
8524511, Sep 3, 2013
Filed:
Aug 10, 2012
Appl. No.:
13/571675
Inventors:
Tom Zhong - Saratoga CA, US
Vinh Lam - Roseville CA, US
Zhongjian Teng - Santa Clara CA, US
Assignee:
Headway Technologies, Inc. - Milpitas CA
International Classification:
H01L 21/00
US Classification:
438 3, 438637, 257421, 257E29323
Abstract:
A CMOS device is provided in a substrate. A magnetic tunnel junction (MTJ) is provided over the CMOS device and connected to the CMOS device by a metal ring contact wherein a dielectric or other filling material forms the center of the metal ring contact and wherein a bottom of the metal ring contact underlying said filling material is metal.

Mtj Device Performance By Adding Stress Modulation Layer To Mtj Device Structure

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US Patent:
20220384713, Dec 1, 2022
Filed:
Aug 10, 2022
Appl. No.:
17/885079
Inventors:
- Hsin-Chu, TW
Tom Zhong - Saratoga CA, US
Vinh Lam - Dublin CA, US
Vignesh Sundar - Sunnyvale CA, US
Zhongjian Teng - Santa Clara CA, US
International Classification:
H01L 43/02
H01L 43/12
G11B 19/20
G11B 5/60
G11B 5/48
G11B 5/39
Abstract:
A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

Mtj Device Performance By Controlling Device Shape

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US Patent:
20230107977, Apr 6, 2023
Filed:
Dec 12, 2022
Appl. No.:
18/064808
Inventors:
- Hsin-Chu, TW
Tom Zhong - Saratoga CA, US
Zhongjian Teng - Santa Clara CA, US
Vinh Lam - Dublin CA, US
Yi Yang - Fremont CA, US
International Classification:
H01L 43/12
H01F 10/06
H01F 10/16
H01L 43/02
H01L 43/08
H01L 43/10
Abstract:
A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

Mtj Device Performance By Adding Stress Modulation Layer To Mtj Device Structure

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US Patent:
20200075844, Mar 5, 2020
Filed:
Nov 11, 2019
Appl. No.:
16/679498
Inventors:
- Hsinchu, TW
Tom Zhong - Saratoga CA, US
Vinh Lam - Dublin CA, US
Vignesh Sundar - Sunnyvale CA, US
Zhongjian Teng - Santa Clara CA, US
International Classification:
H01L 43/02
G11B 5/48
G11B 5/60
G11B 19/20
H01L 43/12
Abstract:
A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

Computing Interface System

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US Patent:
20190346940, Nov 14, 2019
Filed:
Jul 22, 2019
Appl. No.:
16/518912
Inventors:
- San Jose CA, US
Vinh Vi Lam - San Jose CA, US
Frank Peter Lambrecht - Danville CA, US
Assignee:
Opdig, Inc. - San Jose CA
International Classification:
G06F 3/0346
G06F 3/01
G06F 3/023
Abstract:
Computing interface systems and methods are disclosed. Some implementations include a first accelerometer attached to a first fastening article that is capable of holding the first accelerometer in place on a portion of a thumb of a user. Some implementations may also include a second accelerometer attached to a second fastening article that is capable of holding the second accelerometer in place on a portion of a wrist of a user. Some implementations may additionally or alternatively include magnetometers and/or gyroscopes attached to the first and second fastening articles. Some implementations may also include a processing device configured to receive measurements from the accelerometers, magnetometers, and/or gyroscopes and identify, based on the measurements, symbols associated with motions of a user's hand and/or the orientation of the hand. Some implementations may allow a user to control a cursor in a three dimensional virtual space and interact with objects in that space.

Method For Fabricating A Magnetic Tunneling Junction (Mtj) Structure

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US Patent:
20190341542, Nov 7, 2019
Filed:
May 1, 2018
Appl. No.:
15/968035
Inventors:
- Hsinchu, TW
Tom Zhong - Saratoga CA, US
Vinh Lam - Dublin CA, US
Vignesh Sundar - Sunnyvale CA, US
Zhongjian Teng - Santa Clara CA, US
International Classification:
H01L 43/02
H01L 43/12
G11B 5/48
G11B 5/60
G11B 19/20
Abstract:
A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

Mtj Device Performance By Controlling Device Shape

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US Patent:
20190148630, May 16, 2019
Filed:
Nov 13, 2017
Appl. No.:
15/810494
Inventors:
- Milpitas CA, US
Tom Zhong - Saratoga CA, US
Zhongjian Teng - Santa Clara CA, US
Vinh Lam - Dublin CA, US
Yi Yang - Fremont CA, US
International Classification:
H01L 43/12
H01L 43/02
H01L 43/08
H01L 43/10
H01F 10/06
H01F 10/16
Abstract:
A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

Distributed Bandwidth Allocation And Throttling

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US Patent:
20180091436, Mar 29, 2018
Filed:
Aug 25, 2017
Appl. No.:
15/686318
Inventors:
- Mountain View CA, US
Vinh The Lam - Milpitas CA, US
Kirill Mendelev - Sunnyvale CA, US
Li Shi - San Mateo CA, US
International Classification:
H04L 12/911
H04L 12/825
H04L 12/26
Abstract:
A distributed bandwidth allocation system a distributed bandwidth limiter, a first throttler, and a second throttler. The distributed bandwidth limiter receives first usage data for a first entity and usage data for a second entity. Based on the first usage data, second usage data, and a total bandwidth allocation, the distributed bandwidth limiter determines a first bandwidth allocation specifying bandwidth available for network traffic for the first entity and a second bandwidth allocation that specifies bandwidth available for network traffic for the second entity, wherein a sum of the first bandwidth allocation and the second bandwidth allocation does not exceed the total bandwidth allocation. The first bandwidth allocation and the second bandwidth allocation are provided to respective throttlers than manage traffic for the first and second entities.
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Vinh Xuong Lam from Hayward, CA, age ~63 Get Report