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Vinh D Ho

from San Jose, CA
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Related to:
Hillary D Ho, 54Hong T Tran, 50Thu N Tran, 39Leesa H Tran, 39Quoc Diep Ho, 50Jao Y Sung, 75Thanh V Ho, 43Toan Dang HoLoi Dang Ho, 35Hanh T Ho, 45Quang D Ho, 40Phucthi K Ho, 36Dao D Ho, 77
Connected to:
Adrianne Ho, 38Agnes P Ho, 92Aida Ho, 76Amy Ho, 44Angelina Ho, 43Anita Ho, 53Anne D Ho, 68Anya Ho, 35Baochau V Ho, 41Baotran T Ho, 38

Vinh Ho Phones & Addresses

  • San Jose, CA

Professional Records

License Records

Vinh Dac Ho

License #:
1206009024
Category:
Nail Technician License

Medicine Doctors

Vinh Ho Photo 1

Vinh Ho

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Specialties:
Addiction Medicine
Work:
Aegis Medical SystemAegis Treatment Centers
1322 N Avalon Blvd, Wilmington, CA 90744
(310) 513-1300 (phone), (310) 513-1311 (fax)
Languages:
English
Spanish
Description:
Mr. Ho works in Wilmington, CA and specializes in Addiction Medicine.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vinh Ho
VINH HO INC
Vinh Ho
AV NAIL SPA AUSTIN LANDINGS INC
Vinh Ho
AV NAIL SPA RIDGE HILL INC
Vinh Ho
AV NAIL SPA ST MATTHEWS INC
Vinh Q. Ho
VINH Q HO ENTERPRISES INC
Vinh Ho
TRIEU-HO ENTERPRISES INC

Publications

Us Patents

Leakage Compensation And Improved Setup/Hold Time In A Dynamic Flip-Flop

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US Patent:
7893726, Feb 22, 2011
Filed:
Jul 24, 2007
Appl. No.:
11/782443
Inventors:
Vinh Van Ho - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 19/00
US Classification:
327 57, 327 52, 330252, 330277
Abstract:
A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.

Level Shifter Circuit With A Thin Gate Oxide Transistor

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US Patent:
8049532, Nov 1, 2011
Filed:
Jun 25, 2010
Appl. No.:
12/823596
Inventors:
Simardeep Maangat - Sunnyvale CA, US
Vinh Van Ho - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/0175
H03L 5/00
US Classification:
326 68, 327333
Abstract:
A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.

Multi-Phase Interpolators And Related Methods

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US Patent:
8294500, Oct 23, 2012
Filed:
Nov 18, 2009
Appl. No.:
12/621493
Inventors:
Vinh Van Ho - San Jose CA, US
Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Van Ton-That - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03H 11/16
US Classification:
327231, 327237
Abstract:
A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.

Multi-Purpose Phase-Locked Loop For Low Cost Transceiver

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US Patent:
8619931, Dec 31, 2013
Filed:
Nov 19, 2009
Appl. No.:
12/622152
Inventors:
Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Thungoc M. Tran - San Jose CA, US
Vinh Van Ho - San Jose CA, US
Leon Zheng - San Francisco CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H04L 7/00
US Classification:
375355
Abstract:
Integrated circuits having transceivers capable of high-speed (e. g. , 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

Techniques For Phase Interpolation

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US Patent:
7994837, Aug 9, 2011
Filed:
Aug 7, 2009
Appl. No.:
12/537634
Inventors:
Vinh Van Ho - San Jose CA, US
Tien Duc Pham - San Jose CA, US
Tim Tri Hoang - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03H 11/16
US Classification:
327231, 327233
Abstract:
A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.

High-Speed Level-Shifting Circuit

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US Patent:
7521964, Apr 21, 2009
Filed:
Mar 26, 2007
Appl. No.:
11/691106
Inventors:
Mei Luo - San Jose CA, US
Vinh Van Ho - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/0175
US Classification:
326 68, 326 81, 326115
Abstract:
In level-shifting circuitry for shifting low-voltage-domain signals to a high-voltage domain, one of two output transistors is driven with one of the low-voltage-domain signals, thereby reducing loading on the output and increasing output speed and bandwidth. The circuitry can be mirrored for differential operation. When included in a serial interface of a programmable logic device, the circuitry can be programmably selectable between single-ended and differential operation.
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Vinh D Ho from San Jose, CA Get Report