Van Pham

61001015, Aug 8, 2000

Oct 27, 1998

9/179172

Amit P. Marathe - Santa Clara CA
Nguyen D. Bui - San Jose CA
Van Pham - Milpitas CA

Advanced Micro Devices Inc. - Sunnyvale CA

G01R 3126

438 14

A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0. 1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0. 1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0. 1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0. 1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

63298317, Dec 11, 2001

Aug 8, 1997

8/908794

Nguyen Duc Bui - San Jose CA
Michael Anthony Niederhofer - Milpitas CA
Van Hung Pham - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G01R 3126
G01R 3102

324765

A method and apparatus for monitoring and controlling integrated circuit devices-under-test (DUTS). A preferred embodiment includes a computer based controller, a temperature control module, a power supply controller, a chamber interface module, a driver card and a DUT board. The computer-based controller responding to preprogrammed instructions (software) operates and coordinates the temperature control module, the chamber interface module, the power supply controller, and the driver card. The driver card, receiving commands and data from the computer-based controller, sends and receives a number of signals to and from the DUTs on the DUT board. These signals include voltage sources for operating the DUTs, a load voltage, DC current sources for setting duty and frequency cycles, switch signals, voltage measurement signals, and resistance measurement signals. The DUT board is a printed circuit board for holding a number of DUTs. Each of the DUTs is an integrated circuit containing one or more sets of circuitry for testing specifically designed test structures.

60752939, Jun 13, 2000

Mar 5, 1999

9/263412

Xiao-Yu Li - San Jose CA
Sunil D. Mehta - San Jose CA
Van H. Pham - Milpitas CA
Amit P. Marathe - Santa Clara CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2348

257763

A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.