Resumes
Resumes
Ui Han Phones & Addresses
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Myrtle Beach, SC
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Alpharetta, GA
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Pleasanton, CA
Publications
Us Patents
Verifying Configuration Memory Of A Programmable Logic Device
View pageUS Patent:
7912693, Mar 22, 2011
Filed:
May 1, 2008
Appl. No.:
12/113363
Inventors:
Ui Sun Han - San Jose CA, US
Walter N. Sze - Lake Oswego OR, US
Tsu-Chien Shen - Cupertino CA, US
Walter N. Sze - Lake Oswego OR, US
Tsu-Chien Shen - Cupertino CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 9/00
G06F 9/00
US Classification:
703 14, 703 21, 703 22, 703 24, 710 22
Abstract:
Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.
System And Method For Testing Of Interconnects In A Programmable Logic Device
View pageUS Patent:
7509547, Mar 24, 2009
Filed:
Sep 7, 2005
Appl. No.:
11/220924
Inventors:
Ui Sun Han - Santa Clara CA, US
Walter N. Sze - Lake Oswego OR, US
Walter N. Sze - Lake Oswego OR, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/28
G01R 27/28
G01R 31/00
G01R 31/14
G11C 29/00
G06F 17/50
G06F 9/45
G06F 9/455
H03K 17/693
H03K 19/00
G01R 27/28
G01R 31/00
G01R 31/14
G11C 29/00
G06F 17/50
G06F 9/45
G06F 9/455
H03K 17/693
H03K 19/00
US Classification:
714725, 714724, 714742, 714719, 714736, 714737, 714733, 714734, 716 17, 716 16, 716 18, 716 8, 716 10, 716 12, 702117, 702118, 702119, 702120
Abstract:
Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.
Boundary Logic Interface
View pageUS Patent:
20200274536, Aug 27, 2020
Filed:
Feb 26, 2019
Appl. No.:
16/285588
Inventors:
- San Jose CA, US
Ui S. Han - San Jose CA, US
Weiguang Lu - San Jose CA, US
Ui S. Han - San Jose CA, US
Weiguang Lu - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/177
G06F 17/50
G06F 17/50
Abstract:
Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.