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Tom C Chi

from Grand Rapids, MI
Age ~70
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Also known as:
Tj Chi, Rene Hsueh Chi, Thomas C Chi, Terrence C Chi, Renee H Chi, Chi Tj, Chi Rene, Rene Hchi, Hsuehing Yang
Related to:
Nancy F Chang
Connected to:
Allen H Chi, 41Angelica Chi, 28Bradd S Chi, 54Catherine C Chi, 53Chang H Chi, 90Christin Chi, 41Christie Y Chi, 28Christy S Chi, 77Clifford Y Chi, 40Cristina Chi, 54

Tom Chi Phones & Addresses

  • Grand Rapids, MI
  • 3332 70Th St, Jackson Hts, NY 11372 (347) 981-7260
  • Jackson Heights, NY
  • Herndon, VA
  • Yorba Linda, CA
  • Placentia, CA
  • 3332 70Th St, Jackson Hts, NY 11372

Work

Company: Tom chi Address: 11 East Broadway Suite 7D, New York, NY 10038 Phones: (212) 791-1520 Position: President Industries: Business Associations

Education

Degree: High school graduate or higher

Resumes

Resumes

Tom Chi Photo 1

The Pain Whisperer Cures Pain With "A Snap Of The Fingers"

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Location:
Greater New York City Area
Industry:
Medical Practice
Work:
Master Acupuncture - Catskill Mountains, N.Y. 1981 - 2012
Pioneer of Supertouch Therapy and Doctor of Acupuncture
Skills:
Board Certified
Family Medicine
Internal Medicine
Surgery
Emergency Medicine
Urgent Care
Clinical Research
Medical Education
Medicine
Pediatrics
Sports Medicine
Healthcare
Hospitals
Healthcare Management
Treatment
Interests:
invention, design, salsa and west coast swing dancing, Chinese medicine, meditation, kung fu, snowboarding, building, comedy, poetry,
Honor & Awards:
Never paid Who's Who to include me. Doesn't seem sane!
Languages:
Spanish
Tom Chi Photo 2

Tom Chi

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Location:
Jackson Heights, NY
Industry:
Import And Export
Tom Chi Photo 3

Maintenance

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Industry:
Machinery
Work:
United States Postal Service
Maintenance
Tom Chi Photo 4

Tom Chi

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Tom Chi Photo 5

Tom Chi

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Tom Chi Photo 6

Tom Chi

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Tom Chi Photo 7

Tom Chi

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Tom Chi
President
Tom Chi
Business Associations
11 East Broadway Suite 7D, New York, NY 10038
Tom Chi
President
ANCOM INC
22775 Ln Palma Ave, Yorba Linda, CA 92887
Tom Chi
President
IMPERIAL SUPPLIES, INC
22775 Ln Palma Ave, Yorba Linda, CA 92887
Tom Chi
President
Tom Chi
Business Associations
11 East Broadway Suite 7D, New York, NY 10038

Publications

Us Patents

Bonding Of Integrated Circuit Chip To Carrier Using Gold/Tin Eutectic Alloy And Refractory Metal Nitride Barrier Layer To Block Migration Of Tin Through Via Holes

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US Patent:
53789261, Jan 3, 1995
Filed:
Jan 10, 1994
Appl. No.:
8/179898
Inventors:
Tom Y. Chi - San Gabriel CA
Brook D. Raymond - Hermosa Beach CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2348
H01L 2962
H01L 2940
US Classification:
257767
Abstract:
A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16, 18) formed on a frontside surface (12a), and via holes (12c, 12d) formed through the chip (12) from the frontside surface (12a) to a backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c, 12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold-tin alloy (20) through the via holes (12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16, 18).

Method Of Fabricating A Self-Aligned Double Recess Gate Profile

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US Patent:
55567975, Sep 17, 1996
Filed:
May 30, 1995
Appl. No.:
8/453676
Inventors:
Tom Y. Chi - San Gabriel CA
Liping D. Hou - Rancho Palos Verdes CA
Kusol Lee - Gardena CA
Danny Li - Torrance CA
Ishver K. Naik - Rancho Palos Verdes CA
Tom Quach - Torrance CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 218258
US Classification:
437405
Abstract:
A method of fabricating a self-aligned double gate recess profile in a semiconductor substrate is disclosed in which a first mask layer is formed over the substrate. A second mask layer having an opening is formed over the first mask layer. An opening at least as wide as the second mask layer's opening is formed through the first mask layer to expose the substrate beneath the second mask layer's opening. A first recess is etched in the semiconductor through the second mask layer's opening. The first mask layer's opening is then uniformly expanded and a wider recess, aligned to the first recess, is then formed in the semiconductor. The method is particularly applicable to the formation of self-aligned gate and channel recesses in a GaAs MESFET.

Maskless Process For Forming Refractory Metal Layer In Via Holes Of Gaas Chips

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US Patent:
53506626, Sep 27, 1994
Filed:
Jan 13, 1994
Appl. No.:
8/181371
Inventors:
Tom Y. Chi - San Gabriel CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
G03F 720
US Classification:
430313
Abstract:
A "maskless" process is provided for the formation of a refractory metal layer (22b), such as titanium, in via holes (18) through GaAs wafers (12) to contact microwave monolithic integrated circuit (MMIC) devices (10) formed on the front surface (12a) thereof. The process of the invention, which prevents AuSn solder (28) from filling up the holes during a subsequent eutectic AuSn bonding of the device to a metal carrier (30), such as molybdenum, utilizes the difference of resist thickness on the GaAs backside surface (12b) and in the via holes, so that the resist (24b) remaining in the via holes after removing the resist (24a) over the GaAs back surface serves as a mask in etching the refractory metal layer (22a) over the GaAs back surface. The process of the invention does not require any masks, and results in self-alignment of the refractory metal to the via hole. The process is simple and results in high yield of the MMIC devices on GaAs chips (26).

Dual Etchant Process, Particularly For Gate Recess Fabrication In Gaas Mmic Chips

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US Patent:
54362016, Jul 25, 1995
Filed:
May 28, 1993
Appl. No.:
8/068871
Inventors:
Tom Y. Chi - San Gabriel CA
Danny Li - Torrance CA
Liping Hou - Rancho Palos Verdes CA
Tom Quach - Torrance CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 218252
US Classification:
437203
Abstract:
A semiconductor substrate is etched in a two-step sequence, with two different liquid etchants that have different lateral etch rates. The relative time periods for which the etchants are applied are selected to achieve a close match between the actual etch profile and the desired profile. The process is particularly applicable to the formation of a gate recess in a GaAs MESFET for high power amplification.

Field-Effect Transistor With High Breakdown Voltage Provided By Channel Recess Offset Toward Drain

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US Patent:
55392288, Jul 23, 1996
Filed:
Feb 7, 1995
Appl. No.:
8/385386
Inventors:
Tom Y. Chi - San Gabriel CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2980
H01L 31112
US Classification:
257283
Abstract:
A monolithic-microwave-integrated-circuit (MMIC) metal-semiconductor-field-effect (MESFET) transistor (40) or other type of field-effect transistor has a double-recessed channel region (32,42) with a gate recess (42) formed in a channel recess (32). The channel recess (32) is offset toward the drain (16) as far as possible without shorting the channel recess (32) to the drain (16) to increase the transistor breakdown voltage. The gate recess (42) is offset toward the source (14) as far as possible without causing the gate-source capacitance to increase, thereby reducing the transistor source resistance.

Bonding Of Integrated Circuit Chip To Carrier Using Gold/Tin Eutectic Alloy And Refractory Metal Barrier Layer To Block Migration Of Tin Through Via Holes

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US Patent:
51569981, Oct 20, 1992
Filed:
Sep 30, 1991
Appl. No.:
7/767949
Inventors:
Tom Y. Chi - San Gabriel CA
Brook D. Raymond - Hermosa Beach CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H01L 2158
US Classification:
437209
Abstract:
A gallium arsenide monolithic microwave integrated circuit (MMIC) chip (12) has microelectronic devices (16,18) formed on a frontside surface (12a), and via holes (12c,12d) formed through the chip (12) from the frontside surface (12a) to the backside surface (12b). The backside surface (12b) of the chip (12) is bonded to a molybdenum carrier (14) by an eutectic gold/tin alloy (20). A barrier layer (22) including a refractory metal nitride material (22a) is sputtered onto the backside surface (12b) and into the via holes (12c,12d) of the chip (12) prior to bonding. The barrier layer (22) blocks migration of tin from the eutectic gold/tin alloy (20) through the via holes 12c,-12d) to the frontside surface (12a) of the chip (12) during the bonding operation, thereby preventing migrated tin from adversely affecting the microelectronic devices (16,18 ).
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Tom C Chi from Grand Rapids, MI, age ~70 Get Report