Search

Tho Le La

from San Jose, CA
Age ~56
Get Report
Also known as:
Tho L La, Tho T La, Tho L Lela, Thi La, Pho La, Le La Tho, La T Ho, La Pho
Phone and address:
1566 Nobu Dr, San Jose, CA 95131
Related to:
Jean L Smith, 80Tam T Le, 57Thanh Le, 57Christine T Le, 49Vu H Ho, 52Kathy Ho, 75
Connected to:
Ada La, 28Bay C La, 71Belkis G La, 56Bernard R La, 56Binh La, 46Cavera J La, 79Celia J La, 47Colleen La, 70Crosse L La, 78Dan Q La, 63

Tho La Phones & Addresses

  • 1566 Nobu Dr, San Jose, CA 95131
  • San Diego, CA
  • Sunnyvale, CA

Publications

Us Patents

Interlevel Dielectric Thickness Monitor For Complex Semiconductor Chips

View page
US Patent:
6350627, Feb 26, 2002
Filed:
Apr 13, 2000
Appl. No.:
09/548741
Inventors:
Tho Le La - San Jose CA
John Jianshi Wang - San Jose CA
Hao Fang - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3126
US Classification:
438 14, 438692, 257 48
Abstract:
A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box. Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.

Method Of Inspecting A Semiconductor Wafer For Defects

View page
US Patent:
6403385, Jun 11, 2002
Filed:
Jan 27, 1998
Appl. No.:
09/014130
Inventors:
Subramanian Venkatkrishnan - Sunnyvale CA
Tho L. La - San Jose CA
Pei-Yuan Gao - San Jose CA
Richard Lamm - Union City CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2166
US Classification:
438 14, 438 16, 438692, 438693, 438706, 438745, 438959
Abstract:
A method of decorating a semiconductor substrate with an etchant solution is provided for revealing defects, such as microscratches, resulting from an oxide chemical-mechanical planarization (CMP) polishing. An oxide layer is provided over the substrate made from, for example, tetraethylorthosilicate (TEOS). The oxide layer is polished by a CMP process which tends to leave behind microscratches and other defects that can cause conductivity problems on the wafer. To reveal the microscratches, the wafer is decorated or submerged in an etchant, such as an HF etchant, for a period of time. Following the decorating, the wafer is rinsed, dried and inspected. The method improves the ability to identify and optimize steps in a semiconductor fabrication process that cause semiconductor defects.

Methods And Circuits For Testing A Circuit Fabrication Process For Device Uniformity

View page
US Patent:
6507942, Jan 14, 2003
Filed:
Jul 11, 2000
Appl. No.:
09/613494
Inventors:
Anthony P. Calderone - San Jose CA
Feng Wang - San Jose CA
Tho Le La - San Jose CA
Assignee:
Xilinx , Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 16, 716 17, 716 18
Abstract:
Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.

Backside Wafer Polishing For Improved Photolithography

View page
US Patent:
57802041, Jul 14, 1998
Filed:
Feb 3, 1997
Appl. No.:
8/790886
Inventors:
Tho Le La - San Jose CA
Subramanian Venkatkrishnan - Sunnyvale CA
Mark T. Ramsbey - Sunnyvale CA
Jack F. Thomas - Palo Alto CA
Kathleen Early - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G03C 500
G03F 700
US Classification:
430312
Abstract:
The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by polishing the wafer backside prior to photolithography. It was found that particles adhering to and/or scratches on the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Backside polishing, as by chemical-/mechanical polishing, removes such adhering particles and/or scratches, thereby improving photolithographic accuracy.

Defect Management System For Productivity And Yield Improvement

View page
US Patent:
57610649, Jun 2, 1998
Filed:
Oct 6, 1995
Appl. No.:
8/539913
Inventors:
Tho Le La - San Jose CA
Ying Shiau - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1900
US Classification:
36446817
Abstract:
An automated wafer defect management system in which wafer defect data are collected from wafer inspection instruments, converted into a standard data format and made available through a central database system to workstations for review, analysis, and evaluation.

Doubled-Sided Wafer Scrubbing For Improved Photolithography

View page
US Patent:
61365106, Oct 24, 2000
Filed:
Feb 13, 1997
Appl. No.:
8/800940
Inventors:
Tho Le La - San Jose CA
Subramanian N. Venkatkrishnan - Sunnyvale CA
Mark T. Ramsbey - Sunnyvale CA
Jack F. Thomas - Palo Alto CA
Kathleen Regina Early - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G03F 700
US Classification:
430313
Abstract:
The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.

Interlevel Dielectric Thickness Monitor For Complex Semiconductor Chips

View page
US Patent:
6072191, Jun 6, 2000
Filed:
Dec 16, 1997
Appl. No.:
8/991299
Inventors:
Tho Le La - San Jose CA
John Jianshi Wang - San Jose CA
Hao Fang - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2358
H01L 214763
US Classification:
257 48
Abstract:
A method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of the plurality of monitor boxes, wherein said thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box. Also disclosed is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on said surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
Control profile
Tho Le La from San Jose, CA, age ~56 Get Report