Tam T Tran

6515910, Feb 4, 2003

Feb 15, 2002

10/076826

Peter W. Lee - Saratoga CA
Hsing-Ya Tsao - San Jose CA
Tam Tran - San Jose CA
Fu-Chang Hsu - San Jose CA

Aplus Flash Technology Inc. - San Jose CA

G11C 1606

36518522, 36518529, 3651853, 36518509

A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.

6563742, May 13, 2003

Mar 4, 2002

10/090356

Peter W. Lee - Saratoga CA
Tam H. Tran - San Jose CA

Aplus Flash Technology, Inc. - San Jose CA

G11C 1600

36518529, 365 63, 36518522

A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided. The VNN pin is, preferably, multiplexed with the chip enable bar (CEB) pin.

6731564, May 4, 2004

Mar 18, 2003

10/391006

Tam M. Tran - Austin TX
George B. Jamison - Murphy TX
Bryan D. Sheffield - Rowlett TX
David J. Toops - Terrell TX
Vikas K. Agrawal - Dallas TX

Texas Instruments Incorporated - Dallas TX

G11C 700

365229, 365227, 365203

According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

6943617, Sep 13, 2005

Dec 29, 2003

10/748540

Hieu Van Tran - San Jose CA, US
Tam Huu Tran - San Jose CA, US
Vishal Sarin - Santa Clara CA, US
Anh Ly - San Jose CA, US
Niang Hangzo - San Jose CA, US
Sang Thanh Nguyen - Union City CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G05F001/10

327539

A bandgap reference generator comprises a PMOS transistor and NMOS transistor in a pnp bipolar junction transistor connected in series in a first leg. The bandgap reference generator includes a second leg that includes a PMOS transistor, an NMOS transistor, a resistor and a pnp bipolar junction transistor. A bias circuit provides a bias to a mirror formed by the gates of the PMOS transistors to lower the operating voltage of the bandgap reference generator. A second biasing circuit may provide bias to the mirror formed of the NMOS transistors. A time-based and a DC bias-based start up circuitry and method is provided.

6956398, Oct 18, 2005

Mar 23, 2004

10/806624

Hugh Mair - Fairview TX, US
Luan A. Dang - Richardson TX, US
Xiaowei Deng - Plano TX, US
George B. Jamison - Murphy TX, US
Tam M. Tran - Austin TX, US
Shyh-Horng Yang - Plano TX, US
David B. Scott - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H03K017/16

326 33, 326 17, 326112, 326119

The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

6965261, Nov 15, 2005

Nov 13, 2003

10/712198

Tam Minh Tran - Austin TX, US
George B. Jamison - Murphy TX, US

Texas Instruments Incorporated - Dallas TX

H03K003/289

327202, 327203

An embodiment of a ultra low-power data retention latch circuit involves a slave latch SL that concurrently latches the same data that is loaded into a main circuit (such as a main latch ML) during normal operation. When the circuit enters a low power (data retention) mode, power (VCC) to the main latch ML is removed and the slave latch SL retains the most recent data (retained data SA, SA-). When power is being restored to the main latch ML, the slave latch's retained data SA, SA- is quickly restored to the main latch ML through what constitute Set and Reset inputs SAR, SAR- of the ML. This arrangement ensures that data restoration is much quicker than conventional arrangements that require the output data path DATA- to be stabilized before power is re-applied to the main latch. Further, there is no need to wait for power to the ML to be stable before restoring data from the SL to the ML, providing an increase in data restoration speed over conventional data retention latches. Using retained data SA, SA- (as mirrored in SAR, SAR-) to control the Set and Reset inputs prevents data contention in the main latch ML.

7152187, Dec 19, 2006

Nov 26, 2003

10/723377

Tam Minh Tran - Austin TX, US
George B. Jamison - Murphy TX, US

Texas Instruments Incorporated - Dallas TX

G06F 11/00

714 42, 714 5, 714 54, 714710, 714718, 365200, 365201, 365226, 365228, 713324

A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains power to the repair registers and minimal control logic in the memories, while all other circuitry can be either placed in a low power data retention mode, or completely powered off. There is no need to rescan the repair data from the E-fuse farm after one or more memories are powered back up. This provides dynamic power savings since there is no longer any need to idle the system to reload repair data. Since the E-fuse farm can be powered down after initial system power-up and repair data is loaded into the memories, there is also a significant leakage power savings.

7454634, Nov 18, 2008

Mar 2, 2005

11/070481

Timothy Donovan - Livermore CA, US
Shafiq Jamal - Gilroy CA, US
Yonghua Song - Cupertino CA, US
Chia-Chun Chung - San Jose CA, US
Tam Tran - San Ramon CA, US
Lawrence Tse - Fremont CA, US

Marvell International Ltd. - Hamilton

G06F 1/32

713322, 713323

A wireless network device having active and inactive modes comprises a clock generating module that generates a first clock signal having a first clock rate. A voltage supply module generates a first voltage level and a second voltage level that is less than the first voltage level. A first digital module receives the first clock rate and the first voltage level during the active mode, receives the second voltage level during the inactive mode and does not receive the first clock signal during the inactive mode. A first analog module communicates with the voltage supply module and has reduced current consumption during the inactive mode.