Tak Lee Phones & Addresses
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Laguna Woods, CA
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Clint, TX
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7613 Pats Branch Dr, Raleigh, NC 27612 (919) 326-7431
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1205 Condor Dr, Greensboro, NC 27410 (336) 299-2521
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Winston Salem, NC
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Alhambra, CA
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Wade, NC
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7613 Pats Branch Dr, Raleigh, NC 27612
Work
Position:
Retired
Education
Degree:
Associate degree or higher
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
TRANS AIR INTERNATIONAL (U.S.A.) CORPORATION
Managing
Tbn Fund I, LLC
Investment
Investment
17785 Ctr Ct Dr N, Artesia, CA 90703
Publications
Isbn (Books And Publications)
Five-Lipoxygenase Products in Asthma
View page
Author
Tak H. Lee
ISBN #
0824701674
Us Patents
System And Method For Interleaving Data In A Communications Device
View pageUS Patent:
7073012, Jul 4, 2006
Filed:
Aug 26, 2003
Appl. No.:
10/647526
Inventors:
Tak K Lee - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 12/06
H03M 13/00
H03M 13/00
US Classification:
711 5, 711157, 714752, 714762
Abstract:
A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which is coupled to the memory. The system also includes a interleaving logic module coupled to the read and write modules. The interleaving logic module determines an interleaving sequence comprising a sequence of memory addresses. Each memory address is then communicated sequentially to the read and write modules. When the read module receives the address, the read module reads the stored data symbol. When the write module receives the address, the write module writes a symbol from a next data block to the vacated address. The interleaving logic module repeats these steps until every symbol of the stored block has been read and every symbol of the next data block has been written to memory.
All Digital Reference Frequency Locking
View pageUS Patent:
7203227, Apr 10, 2007
Filed:
Nov 14, 2002
Appl. No.:
10/294048
Inventors:
Bruce J. Currivan - Irvine CA, US
Ravi Bhaskaran - Irvine CA, US
Thomas J. Kolze - Phoenix AZ, US
Kevin Lee Miller - Lawrenceville GA, US
Jeffrey S. Putnam - Irvine CA, US
Fang Lu - Rowland Heights CA, US
Tak K. Lee - Irvine CA, US
Thuji S. Lin - Irvine CA, US
Loke Kun Tan - Irvine CA, US
Gopal Triplicane Venkatesan - Aliso Viejo CA, US
Hsin-An Liu - Irvine CA, US
Jonathan S. Min - Buena Park CA, US
James P. Cavallo - Laguna Niguel CA, US
Ravi Bhaskaran - Irvine CA, US
Thomas J. Kolze - Phoenix AZ, US
Kevin Lee Miller - Lawrenceville GA, US
Jeffrey S. Putnam - Irvine CA, US
Fang Lu - Rowland Heights CA, US
Tak K. Lee - Irvine CA, US
Thuji S. Lin - Irvine CA, US
Loke Kun Tan - Irvine CA, US
Gopal Triplicane Venkatesan - Aliso Viejo CA, US
Hsin-An Liu - Irvine CA, US
Jonathan S. Min - Buena Park CA, US
James P. Cavallo - Laguna Niguel CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 1/38
US Classification:
375222
Abstract:
All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10. 24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.
Asynchronous Circuit Design Tool And Computer Program Product
View pageUS Patent:
7418676, Aug 26, 2008
Filed:
Jan 19, 2005
Appl. No.:
11/037139
Inventors:
Nobuo Karaki - Matsumoto, JP
Tak Kwan Lee - Irvine CA, US
Tak Kwan Lee - Irvine CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
G06F 17/50
US Classification:
716 3
Abstract:
It is the object of the present invention to provide asynchronous circuit design tools for those engineers who are versed in standard hardware description languages (HDLs), which is widely used in industry mainly for synchronous circuit design, to design asynchronous circuits with relative ease. To accomplish the object, the asynchronous circuit design tools of the present invention include a translator for transforming a code written in an asynchronous circuit design language, which is based on a standard HDL and includes minimal primitives for describing the communications between asynchronous circuit blocks or processes, into a code written in a standard HDL, which is originally developed for synchronous circuit design. The codes transformed into the standard HDL can be functionally verified by using commercially available simulators, which are originally developed for verifying synchronous circuit design.
Multi-Dimensional Space Gray Code Maps For Multi-Dimensional Phase Modulation As Applied To Ldpc (Low Density Parity Check) Coded Modulation
View pageUS Patent:
7436902, Oct 14, 2008
Filed:
Jun 12, 2004
Appl. No.:
10/866542
Inventors:
Tak K. Lee - Irvine CA, US
Kelly Brian Cameron - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Kelly Brian Cameron - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 27/20
H04L 27/18
H04L 5/12
H04L 27/18
H04L 5/12
US Classification:
375308, 375279, 375302, 375280, 375265
Abstract:
Multi-dimensional space Gray code maps for multi-dimensional phase modulation as applied to LDPC (Low Density Parity Check) coded modulation. A novel approach is provided within LDPC coded modulation communication systems that employ multi-dimensional phase modulation, using m-D (multi-dimensional) Gray code maps, to provide for improved performance when compared to communication systems employing 1-D (single-dimensional) Gray code maps. This approach can generate all possible m-D Gray code maps for a 2m-D M PSK modulation system. For example, all of the 2-D Gray code maps may be generated for a communication system using 4-D 8 PSK modulation system (where m=2, and M=8). A variety decoding processing approaches may be employed to perform LDPC coded modulation decoding of multi-dimensional space Gray code mapped signals. The slightly increased decoding complexity (when compared to decoding 1-D Gray code mapped signals) is the computation of symbol metrics and their decomposition to bit metrics.
Sub-Matrix-Based Implementation Of Ldpc (Low Density Parity Check) Decoder
View pageUS Patent:
7530002, May 5, 2009
Filed:
Feb 23, 2006
Appl. No.:
11/360267
Inventors:
Tak K. Lee - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Kelly Brian Cameron - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Kelly Brian Cameron - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 13/00
US Classification:
714758, 714752
Abstract:
Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing bit node processing, 1 or more sub-matrices in a column are processed; when performing check node processing, 1 or more sub-matrices in a row are processed. If desired, when performing bit node processing, the sub-matrices in each column are successively processed together (e. g. , all column sub-matrices, all column sub-matrices, etc. ). Analogously, when performing check node processing, the sub-matrices in each row can be successively processed together (e. g. , all row sub-matrices, all row sub-matrices in row , etc. ).
Construction Of Irregular Ldpc (Low Density Parity Check) Codes Using Rs (Reed-Solomon) Codes Or Grs (Generalized Reed-Solomon) Code
View pageUS Patent:
7549105, Jun 16, 2009
Filed:
Nov 2, 2005
Appl. No.:
11/264997
Inventors:
Kelly Brian Cameron - Irvine CA, US
Tak K. Lee - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Tak K. Lee - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 13/00
US Classification:
714755, 714786, 714784, 714756
Abstract:
Construction of Irregular LDPC (Low Density Parity Check) codes using RS (Reed-Solomon) codes or GRS (Generalized Reed-Solomon) codes. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. The corresponding LDPC matrix of such an irregular LDPC code may be constructed by performing partial-matrix processing (including decomposition and partial-matrix replacement thereof) of a parity check matrix that corresponds to a GRS-based regular LDPC code. Such an irregular LDPC code may be appropriately designed using these principles thereby generating a code that is suitable for use in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE (Institute of Electrical & Electronics Engineers) 802. 11n Task Group (i. e. , the Task Group that is working to develop a standard for 802.
System And Method For Adjusting The Phase Of A Frequency-Locked Clock
View pageUS Patent:
7590212, Sep 15, 2009
Filed:
Aug 24, 2007
Appl. No.:
11/892607
Inventors:
Tak K. Lee - Irvine CA, US
Jeffrey S. Putnam - Irvine CA, US
James P. Cavallo - Laguna Niguel CA, US
Jeffrey S. Putnam - Irvine CA, US
James P. Cavallo - Laguna Niguel CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03D 3/24
US Classification:
375376, 375373, 375371, 375357, 375327, 327155, 327156
Abstract:
A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.
Implementation Of Ldpc (Low Density Parity Check) Decoder By Sweeping Through Sub-Matrices
View pageUS Patent:
7617433, Nov 10, 2009
Filed:
Feb 23, 2006
Appl. No.:
11/360268
Inventors:
Tak K. Lee - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Kelly Brian Cameron - Irvine CA, US
Hau Thien Tran - Irvine CA, US
Kelly Brian Cameron - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H03M 13/00
US Classification:
714752, 714758
Abstract:
Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e. g. , all 1columns in 1 or more sub-matrices, all 2columns in 1 or more sub-matrices, etc. ). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e. g. , all 1rows in 1 or more sub-matrices, all 2rows in 1 or more sub-matrices, etc. ).