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Tai H Ly

from Daly City, CA
Age ~37
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Also known as:
Tai Hly
Phone and address:
30 Harbor Dr, Daly City, CA 94014
Related to:
Bora S Ly, 43Hue T Ly, 63Tara Thuy Thanh Hoang, 42Van T Truong, 52Tia T Ly, 45Sanh T Ly, 59Chanhthi T Ly, 48Quich H Ly, 54Ly Bora, 43
Connected to:
Amadou T Ly, 70Amber A Ly, 46Asia N Ly, 46Brannon D Ly, 53Bunlim Ly, 46Bunna N Ly, 69Bunthoeun Ly, 65Carole Ly, 54Caroline T Ly, 44

Tai Ly Phones & Addresses

  • 30 Harbor Dr, Daly City, CA 94014
  • San Francisco, CA

Resumes

Resumes

Tai Ly Photo 1

Technical Support Engineer

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Location:
485 Archglen Way, San Jose, CA 95111
Industry:
Medical Devices
Work:
Auris Health, Inc
Technical Support Engineer
Restoration Robotics Aug 2017 - May 2019
Senior Technical Support Engineer
Restoration Robotics Sep 2015 - Aug 2017
Technical Support Engineer
Accuray Feb 2014 - Sep 2015
Technical Support Engineer
Accuray Jan 2007 - Jan 2010
Systems Installation Engineer
Education:
San Jose State University 2010 - 2012
Bachelors, Bachelor of Arts, Economics, Finance
Skills:
Troubleshooting
Customer Service
Cross Functional Team Leadership
Analysis
Microsoft Office
Management
Microsoft Excel
Access
Medical Devices
Interests:
Mountain Biking
Cooking
Investing
Languages:
English
Tai Ly Photo 2

Operations Manager

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Location:
San Francisco, CA
Industry:
Food Production
Work:
Anresco Laboratories
Operations Manager
Tai Ly Photo 3

Tai Ly

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Location:
San Francisco, CA
Industry:
Hospital & Health Care
Work:
Michael Kors Dec 2014 - Apr 2016
Sale Associated
Tai Ly Photo 4

Systems Installation Technician

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Location:
San Francisco, CA
Industry:
Medical Devices
Work:
Lite-On Americas 2006 - 2007
Technician
Accuray 2006 - 2007
Systems Installation Technician
Education:
San Jose State University
Tai Ly Photo 5

Tai Ly

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Location:
Berkeley, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Peerless Aug 1987 - Mar 2015
R and D Assoc-Prototype
Education:
Chabot College 1980 - 1980
Skills:
Manufacturing
Computer Maintenance
Computer Repair
Troubleshooting
Digital Electronics
Computer Hardware Installation
Solid State Lighting
Network Installation
R&D Model Shop Associate
Fluorescent and Led Lighting System
Electricians
Testing
R&D
Project Management
Design For Manufacturing
Electronics
Product Development
Electrical Wiring
Research and Development
Languages:
English
Cantonese
Vietnamese
Tai Ly Photo 6

Tai Ly

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Tai Ly Photo 7

Tai Ly

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Tai Ly Photo 8

Tai Ly

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Publications

Us Patents

Behavioral Synthesis Links To Logic Synthesis

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US Patent:
6505339, Jan 7, 2003
Filed:
Jan 4, 2000
Appl. No.:
09/476884
Inventors:
Ronald A. Miller - Mountain View CA
Donald B. MacMillen - Redwood Shores CA
Tai A. Ly - San Jose CA
David W. Knapp - Palo Alto CA
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 1750
US Classification:
716 18
Abstract:
A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of A Circuit

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US Patent:
6609229, Aug 19, 2003
Filed:
Aug 9, 2000
Appl. No.:
09/635598
Inventors:
Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada, II - Los Altos CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Ping Fai Yeung - San Jose CA
Assignee:
O-In Design Automation, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 4, 703 14, 703 17
Abstract:
A programmed computer generates descriptions of circuits (called âcheckersâ) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuits description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuits description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit

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US Patent:
6885983, Apr 26, 2005
Filed:
May 4, 2001
Appl. No.:
09/849005
Inventors:
Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul Il Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
Assignee:
Mentor Graphics Corporation - Wilsonville OR
International Classification:
G06F017/50
US Classification:
703 14, 703 15, 703 16, 716 4
Abstract:
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of Circuit

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US Patent:
7007249, Feb 28, 2006
Filed:
Jan 20, 2003
Appl. No.:
10/348116
Inventors:
Tai An Ly - Fremont CA, US
Jean-Charles Giomi - Menlo Park CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
David Lansing Dill - Redwood City CA, US
Paul II Estrada - Los Alto CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Robert Kristianto Mardjuki - Danville CA, US
Ping Fai Yeung - San Jose CA, US
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 703 13, 703 20, 703 23, 703 28
Abstract:
A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit

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US Patent:
7478028, Jan 13, 2009
Filed:
Jan 12, 2005
Appl. No.:
11/035275
Inventors:
Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul II Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
International Classification:
G06F 17/50
US Classification:
703 14, 703 15, 703 16, 716 4
Abstract:
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit

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US Patent:
62927655, Sep 18, 2001
Filed:
Oct 20, 1997
Appl. No.:
8/954765
Inventors:
Robert Kristianto Mardjuki - Danville CA
David Lansing Dill - Redwood City CA
Jing Chyuarn Lin - Sunnyvale CA
Ping Fai Yeung - San Jose CA
Paul II Estrada - Los Alto CA
Jean-Charles Giomi - Menlo Park CA
Tai An Ly - Fremont CA
Kalyana C. Mulam - San Jose CA
Lawrence Curtis Widdoes - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
Assignee:
O-In Design Automation - San Jose CA
International Classification:
G06F 1750
US Classification:
703 14
Abstract:
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of A Circuit

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US Patent:
61759465, Jan 16, 2001
Filed:
Oct 20, 1997
Appl. No.:
8/955329
Inventors:
Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada - Los Alto CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Lawrence Curtis Widdoes - San Jose CA
Ping Fai Yeung - San Jose CA
Assignee:
O-IN Design Automation - San Jose CA
International Classification:
G06F 1750
G06F 1650
US Classification:
716 4
Abstract:
A programmed computer generates descriptions of circuits (called "checkers") that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Behavioral Synthesis Links To Logic Synthesis

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US Patent:
60262192, Feb 15, 2000
Filed:
May 12, 1995
Appl. No.:
8/440101
Inventors:
Ronald A. Miller - Mountain View CA
Donald B. MacMillen - Redwood Shores CA
Tai A. Ly - San Jose CA
David W. Knapp - Palo Alto CA
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 1900
US Classification:
395500
Abstract:
A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.
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Tai H Ly from Daly City, CA, age ~37 Get Report