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Tai Gia Ly

from Oakland, CA
Age ~57
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Also known as:
Tai G Ly, Ly Tai Gia, Gia Ly, Gia Ly Tai, Ly T Ai, Ly Tai, Tai T
Phone and address:
1672 87Th Ave, Oakland, CA 94621
(510) 562-6963
Related to:
Ann L Chuong, 39Ly Le, 45Xuan T Huynh, 86Binh Lam, 38Lily Ly, 52Nancy D Ly, 31
Connected to:
Amadou T Ly, 70Amber A Ly, 46Asia N Ly, 46Bora S Ly, 43Brannon D Ly, 53Bunlim Ly, 46Bunna N Ly, 69Bunthoeun Ly, 65Carole Ly, 54Caroline T Ly, 44

Tai Ly Phones & Addresses

  • 1672 87Th Ave, Oakland, CA 94621 (510) 562-6963
  • 5415 Cole St, Oakland, CA 94601 (510) 261-4598
  • Hayward, CA
  • San Jose, CA
  • Alameda, CA

Resumes

Resumes

Tai Ly Photo 1

Technical Support Engineer

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Location:
485 Archglen Way, San Jose, CA 95111
Industry:
Medical Devices
Work:
Auris Health, Inc
Technical Support Engineer
Restoration Robotics Aug 2017 - May 2019
Senior Technical Support Engineer
Restoration Robotics Sep 2015 - Aug 2017
Technical Support Engineer
Accuray Feb 2014 - Sep 2015
Technical Support Engineer
Accuray Jan 2007 - Jan 2010
Systems Installation Engineer
Education:
San Jose State University 2010 - 2012
Bachelors, Bachelor of Arts, Economics, Finance
Skills:
Troubleshooting
Customer Service
Cross Functional Team Leadership
Analysis
Microsoft Office
Management
Microsoft Excel
Access
Medical Devices
Interests:
Mountain Biking
Cooking
Investing
Languages:
English
Tai Ly Photo 2

Cnc Machinist Setup And Operator

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Location:
Oakland, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Essai, Inc.
Cnc Machinist Setup and Operator
Tai Ly Photo 3

Tai Ly

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Tai Ly Photo 4

Tai Ly

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Tai Ly Photo 5

Tai Ly

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Tai Ly Photo 6

Tai Ly

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Tai Ly Photo 7

Tai Ly

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Tai Ly Photo 8

Tai Ly San Jose, CA

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Work:
Accuray Inc
Sunnyvale, CA
2007 to 2010
Systems Installation Engineer
Philips & Lite-On Digital Solution USA, Inc
Fremont, CA
2005 to 2007
Project Specialist/Tech Support
Education:
San Jose State University
San Jose, CA
Jan 2010 to Jun 2012
BA in Economics

Publications

Us Patents

Behavioral Synthesis Links To Logic Synthesis

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US Patent:
6505339, Jan 7, 2003
Filed:
Jan 4, 2000
Appl. No.:
09/476884
Inventors:
Ronald A. Miller - Mountain View CA
Donald B. MacMillen - Redwood Shores CA
Tai A. Ly - San Jose CA
David W. Knapp - Palo Alto CA
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 1750
US Classification:
716 18
Abstract:
A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of A Circuit

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US Patent:
6609229, Aug 19, 2003
Filed:
Aug 9, 2000
Appl. No.:
09/635598
Inventors:
Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada, II - Los Altos CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Ping Fai Yeung - San Jose CA
Assignee:
O-In Design Automation, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 4, 703 14, 703 17
Abstract:
A programmed computer generates descriptions of circuits (called âcheckersâ) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuits description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuits description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit

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US Patent:
6885983, Apr 26, 2005
Filed:
May 4, 2001
Appl. No.:
09/849005
Inventors:
Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul Il Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
Assignee:
Mentor Graphics Corporation - Wilsonville OR
International Classification:
G06F017/50
US Classification:
703 14, 703 15, 703 16, 716 4
Abstract:
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of Circuit

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US Patent:
7007249, Feb 28, 2006
Filed:
Jan 20, 2003
Appl. No.:
10/348116
Inventors:
Tai An Ly - Fremont CA, US
Jean-Charles Giomi - Menlo Park CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
David Lansing Dill - Redwood City CA, US
Paul II Estrada - Los Alto CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Robert Kristianto Mardjuki - Danville CA, US
Ping Fai Yeung - San Jose CA, US
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 703 13, 703 20, 703 23, 703 28
Abstract:
A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Metastability Injector For A Circuit Description

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US Patent:
7243322, Jul 10, 2007
Filed:
Jun 1, 2004
Appl. No.:
10/859055
Inventors:
Tai An Ly - San Jose CA, US
Ka Kei Kwok - Milpitas CA, US
Vijaya Vardhan Gupta - San Jose CA, US
Ross Andrew Ander - Los Altos CA, US
Ping Fai Yeung - San Jose CA, US
Neil Patrick Hand - Menlo Park CA, US
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 6
Abstract:
During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

Metastability Injector For A Circuit Description

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US Patent:
7454728, Nov 18, 2008
Filed:
Jun 7, 2007
Appl. No.:
11/759888
Inventors:
Tai An Ly - San Jose CA, US
Ka Kei Kwok - Milpitas CA, US
Vijaya Vardhan Gupta - San Jose CA, US
Ross Andrew Andersen - Los Altos CA, US
Ping Fai Yeung - San Jose CA, US
Neil Patrick Hand - Menlo Park CA, US
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 6
Abstract:
During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit

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US Patent:
7478028, Jan 13, 2009
Filed:
Jan 12, 2005
Appl. No.:
11/035275
Inventors:
Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul II Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
International Classification:
G06F 17/50
US Classification:
703 14, 703 15, 703 16, 716 4
Abstract:
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Methods For Automatically Pipelining Loops

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US Patent:
RE40925, Sep 29, 2009
Filed:
Jun 8, 2000
Appl. No.:
09/590584
Inventors:
Tai A. Ly - San Jose CA, US
David W. Knapp - San Jose CA, US
Ronald A. Miller - Cupertino CA, US
Donald B. Macmillen - Redwood City CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 1
Abstract:
A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.
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Tai Gia Ly from Oakland, CA, age ~57 Get Report