Sung Jun Son

20220208232, Jun 30, 2022

Dec 29, 2020

17/136616

- San Diego CA, US
Rahul BIRADAR - Kalaburgi, IN
Biju MANAKKAM VEETIL - Bengaluru, IN
Po-Hung CHEN - Los Angeles CA, US
Ayan PAUL - San Diego CA, US
Sung SON - San Jose CA, US
Shivendra KUSHWAHA - New Delhi, IN
Ravindra Reddy CHEKKERA - Vemula, IN
Derek YANG - San Diego CA, US

G11C 5/02
G11C 7/10
G11C 7/06
G11C 8/08
G11C 8/10

A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.