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Yu Living Sun

from Alameda, CA
Age ~49
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Also known as:
Sun Te Yu, Yu Chan Sun, Yu U Sun, Yu D Sun, Yuli Chan Sun, Li Chang Yu, Chan Sun Yu, I Sun, Yuli Chang, Yuli Chang-Sun
Phone and address:
2717 5Th St, Alameda, CA 94501
Related to:
Sun YuYuli S Chang, 67Hongwei SunTingyun SunLina Du, 68
Connected to:
Aggie Y Sun, 59Agnes C Sun, 51Aijun Sun, 52Albert Sun, 43Alister C Sun, 50Alys L Sun, 55Amy W Sun, 65Angelina H Sun, 60Angelo C Sun, 50Anne M Sun, 86

Yu Sun Phones & Addresses

  • 2717 5Th St, Alameda, CA 94501
  • Oakland, CA
  • San Francisco, CA
  • 1071 Sunrise Ridge Dr, Lafayette, CA 94549
  • El Dorado Hills, CA
  • Somerset, NJ
  • Hoboken, NJ
  • Township of Washington, NJ

Resumes

Resumes

Yu Sun Photo 1

Yu Sun

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Position:
Business Technology Analyst at Deloitte Consulting
Location:
San Francisco Bay Area
Industry:
Management Consulting
Education:
Stanford University 2006 - 2010
B.A., Economics San Francisco Waldorf High School 2002 - 2006
high school diploma
Yu Sun Photo 2

Principal Engineer At Hitachi Gst

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Location:
San Francisco Bay Area
Industry:
Computer Hardware
Yu Sun Photo 3

Yu Sun

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Location:
San Francisco Bay Area
Industry:
Computer Software
Yu Sun Photo 4

Vp Of Tech Development At Spansion

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Location:
San Francisco Bay Area
Industry:
Sporting Goods
Yu Sun Photo 5

Yu Sun

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Location:
San Francisco Bay Area
Industry:
Computer Software
Yu Sun Photo 6

Yu Sun

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Location:
San Francisco Bay Area
Industry:
Computer Hardware
Yu Sun Photo 7

Yu Sun Hayward, CA

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Work:
Giorgio Armani Group
San Francisco, CA
Feb 2014 to May 2014
Visual Merchandising Intern
Love's Journey Home Textile, co., Jiangsu, China

Sep 2010 to May 2012
Founder
Danyang Aiyuan HomeTextile, co., Jiangsu, China

May 2009 to Aug 2009
Summer Intern, Assistant Marketing Manager
Danyang Daily Newspaper, Jiangsu, China

Jun 2008 to Jul 2008
Summer Intern, Assistant Reporter
Jiangsu University
Zhenjiang, CN
May 2005 to Sep 2007
Undergraduate Literature and Art Director & Host
Education:
Academy of Art University
San Francisco, CA
Master in Fashion Merchandising & Marketing
Jiangsu University
Zhenjiang, CN
Jul 2009
Bachelor's in Graphic Design
Yu Sun Photo 8

Yu Sun

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Yu Juei Sun
President
UNION SUN INTERNATIONAL CORPORATION
431 Mundell Way, Los Altos, CA 94022
Yu Sun
Principal
Lotus and Lily Lian
Business Services at Non-Commercial Site · Nonclassifiable Establishments
2300 Pacific Ave, San Francisco, CA 94115

Publications

Us Patents

Method And System For Providing Reduced-Sized Contacts In A Semiconductor Device

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US Patent:
6342415, Jan 29, 2002
Filed:
Sep 23, 1999
Appl. No.:
09/404395
Inventors:
Angela T. Hui - Fremont CA
Tuan Duc Pham - Santa Clara CA
Mark T. Ramsbey - Sunnyvale CA
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218238
US Classification:
438212, 438213, 438270, 438210, 257308
Abstract:
A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0. 28 microns.

Method Of Making Tungsten Gate Mos Transistor And Memory Cell By Encapsulating

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US Patent:
6346467, Feb 12, 2002
Filed:
Aug 28, 2000
Appl. No.:
09/649027
Inventors:
Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Nagoya, JP
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa
International Classification:
H01L 213205
US Classification:
438594, 438264, 438595
Abstract:
A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

Semiconductor Device With Contacts Having A Sloped Profile

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US Patent:
6369416, Apr 9, 2002
Filed:
Sep 23, 1999
Appl. No.:
09/404394
Inventors:
Angela T. Hui - Fremont CA
Tuan Duc Pham - Santa Clara CA
Mark T. Ramsbey - Sunnyvale CA
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2976
US Classification:
257288, 257296, 257306, 257315, 257368, 257390
Abstract:
A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.

Nitrogen Implant After Bit-Line Formation For Ono Flash Memory Devices

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US Patent:
6403420, Jun 11, 2002
Filed:
Jul 28, 2000
Appl. No.:
09/627664
Inventors:
Jean Yang - Sunnyvale CA
Yider Wu - San Jose CA
Mark Ramsbey - Sunnyvale CA
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438261, 438257, 438264, 438514
Abstract:
A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.

Semiconductor Device With Self-Aligned Contacts Using A Liner Oxide Layer

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US Patent:
6420752, Jul 16, 2002
Filed:
Feb 11, 2000
Appl. No.:
09/502163
Inventors:
Minh Van Ngo - Fremont CA
Yu Sun - Saratoga CA
Fei Wang - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Angela T. Hui - Fremont CA
Mark S. Chang - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29788
US Classification:
257315, 257314, 36518501, 36518526
Abstract:
A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

Non-Volatile Memory Device With Encapsulated Tungsten Gate And Method Of Making Same

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US Patent:
6429108, Aug 6, 2002
Filed:
Aug 31, 2000
Appl. No.:
09/652136
Inventors:
Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Tokyo, JP
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kawasaki
International Classification:
H01L 213205
US Classification:
438587
Abstract:
A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.

Nitride Barrier Layer For Protection Of Ono Structure From Top Oxide Loss In A Fabrication Of Sonos Flash Memory

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US Patent:
6440797, Aug 27, 2002
Filed:
Sep 28, 2001
Appl. No.:
09/966702
Inventors:
Yider Wu - Campell CA
Jean Yee-Mei Yang - Sunnyvale CA
Mark Ramsbey - Sunnyvale CA
Emmanuel H. Lingunis - San Jose CA
Yu Sun - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218247
US Classification:
438261, 438954, 438558
Abstract:
A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Method For Forming A Semiconductor Device With Self-Aligned Contacts Using A Liner Oxide Layer

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US Patent:
6475847, Nov 5, 2002
Filed:
Mar 27, 2002
Appl. No.:
10/109526
Inventors:
Minh Van Ngo - Fremont CA
Yu Sun - Saratoga CA
Fei Wang - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Angela T. Hui - Fremont CA
Mark S. Chang - Los Altos CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218238
US Classification:
438201, 438211, 438257, 257314, 257315
Abstract:
A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
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Yu Living Sun from Alameda, CA, age ~49 Get Report