Michael Joon Choi

20020097682, Jul 25, 2002

Jun 4, 2001

09/873924

Syed Enam - Mission Viejo CA, US
Masoud Djafari - Marina Del Rey CA, US
Duke Tran - Irvine CA, US
R. Smythe - Irvine CA, US
Michael Choi - Los Angeles CA, US
Bo-Shiou Ke - Irvine CA, US
Vi Lee - Los Angeles CA, US

H04L012/26

370/241000, 359/110000

The invention relates to methods and apparatus that provide a low frequency data loop-back in a transceiver to advantageously provide built-in test capability with low overhead. The low frequency loop-back advantageously allows testing of a receiver and a transmitter of the transceiver through a high frequency serial interface while reducing the need to interface to a low frequency interface of the transceiver with expensive and specialized test equipment. One embodiment of the low frequency data loop-back includes a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loop-back test command. In one embodiment, a multiplexer selects between the reference clock signal and the generated clock signal.

20020118704, Aug 29, 2002

Jun 4, 2001

09/873950

Syed Enam - Mission Viejo CA, US
Masoud Djafari - Marina Del Rey CA, US
R. Smythe - Irvine CA, US
Michael Choi - Los Angeles CA, US
Vi Lee - Los Angeles CA, US

H04J003/06

370/503000, 370/518000

The invention relates to methods and apparatus that compare the frequencies of a first clock signal and a second clock signal and reliably provide an indication of whether the frequency relationship between the first clock signal and the second clock signal is within a predetermined range. In one embodiment, the first clock signal is a reference clock signal and the second clock signal is generated from a serial bitstream. The indication can be used to synchronize a voltage controlled oscillator within a phase locked loop to the reference clock signal to thereby keep the phase locked loop within a lock range of a serial bitstream from which the second clock is generated. Embodiments of the invention digitally generate a beat frequency related to a difference in speed between the first clock signal and the second clock signal. The beat frequency is synchronized, advantageously obviating the need to synchronize asynchronous counters as is conventionally done.

20020141515, Oct 3, 2002

Jun 4, 2001

09/873934

Syed Enam - Mission Viejo CA, US
Masoud Djafari - Marina Del Rey CA, US
R. Smythe - Irvine CA, US
Vi Lee - Los Angeles CA, US
Michael Choi - Los Angeles CA, US

H03D001/00

375/340000

The invention relates to methods and apparatus that align serial data so as to provide corresponding parallel data. The methods and apparatus search for framing patterns in demultiplexed serial data and shift the demultiplexed serial data to provide aligned parallel data. Advantageously, embodiments of the invention can operate in real time in a relatively high-frequency optical network, such as SONET. One embodiment of the invention detects a frame pattern and provides a nibble shift output. The nibble shift output is applied to another circuit, such as a phase detector or a voltage controlled oscillator, to shift the demultiplexed serial data by a nibble, i.e., four bits. Shifts of smaller increments, i.e., one bit, two bits, or three bits, are applied to the demultiplexed data within a framing circuit to allow the framing circuit to fully align the parallel data.