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Sean Lu

from Foster City, CA
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Related to:
Wade S Lu, 44Jessica Lu, 78Hsin Yang Lu, 45Jessica Y Lu, 51Siqi Lu, 34Sean Lu Hsin-Yang, 45
Connected to:
Abigail I Lu, 32Aiping Lu, 54Allen C Lu, 46Anjian Lu, 84Anna G Lu, 67Anne B Lu, 72Arnold W Lu, 49Ava Lu, 36Ay K Lu, 54Barbara T Lu, 74

Sean Lu Phones & Addresses

  • Foster City, CA

Resumes

Resumes

Sean Lu Photo 1

Software Development Engineer

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Amazon Web Services
Software Development Engineer
Guidewire Software
Engineering Manager and Technician Lead
Guidewire Software Nov 2012 - Oct 2016
Senior Software Engineer, Globalization
Jobdiva Apr 2007 - Nov 2012
Senior Software Engineer
Tmc Nov 2005 - Apr 2007
Software Developer
Education:
Syracuse University 2004 - 2005
Master of Science, Masters, Management The University of Texas at Austin 2002 - 2004
Master of Science, Masters, Civil Engineering National Taiwan University 1997 - 2001
Bachelors, Bachelor of Science, Civil Engineering
Skills:
Jsp
Javascript
Html
Sql
Css
Jquery
Java
Web Development
Ajax
Mysql
Oracle
Xml
Asp.net
Php
Html 5
Gradle
Rest
Angularjs
Mongodb
Object Oriented Design
Languages:
Mandarin
Certifications:
Certified Scrummaster
Scrum Alliance®

Publications

Us Patents

Techniques For Generating Pvt Compensated Phase Offset To Improve Accuracy Of A Locked Loop

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US Patent:
8237475, Aug 7, 2012
Filed:
Oct 8, 2008
Appl. No.:
12/248031
Inventors:
Pradeep Nagarajan - Santa Clara CA, US
Sean Shau-Tu Lu - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Joseph Huang - Morgan Hill CA, US
Yan Chong - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/06
US Classification:
327158, 327149, 327141, 327155
Abstract:
A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.

Variation Compensation Circuitry For Memory Interface

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US Patent:
8565034, Oct 22, 2013
Filed:
Sep 30, 2011
Appl. No.:
13/249954
Inventors:
Sean Shau-Tu Lu - San Jose CA, US
Joseph Huang - Morgan Hill CA, US
Yan Chong - San Jose CA, US
Pradeep Nagarajan - Santa Clara CA, US
Chiakang Sung - Milpitas CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/00
G11C 7/22
US Classification:
365193, 365194, 36518905, 3652331, 36523311, 36523312
Abstract:
Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data and data strobe signals from system memory during read operations. The memory interface circuitry may include de-skew circuitry and dynamic variation compensation circuitry. The de-skew circuitry may be configured during calibration procedures to reduce skew between the data and data strobe signals. The dynamic variation compensation circuitry may be used in real time to compensate for variations in operating conditions. The dynamic variation compensation circuitry may include a phase generation circuit operable to generate data strobe signals having different phases, an edge detection circuit operable to detect leading/trailing edge failures, a control circuit operable to control a counter, and an adjustable delay circuit that is controlled by the counter and that is operable to properly position the data signal with respect to its corresponding data strobe signal.

Digitally Controlled Delay-Locked Loops

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US Patent:
7746134, Jun 29, 2010
Filed:
Apr 18, 2007
Appl. No.:
11/737116
Inventors:
Sean Shau-Tu Lu - San Jose CA, US
Chiakang Sung - Milpitas CA, US
Joseph Huang - Morgan Hill CA, US
Yan Chong - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03L 7/06
US Classification:
327158, 327149
Abstract:
Digitally controlled delay-locked loops can have a phase detector, control logic, and a delay chain. The control logic generates digital signals in response to an output signal of the phase detector. The delay chain generates a delay that varies in response to the digital signals. In some embodiments, the control logic maintains logic states of the digital signals constant in response to an enable signal to maintain the delay of the delay chain constant in a lock mode of the digitally controlled delay-locked loop. In other embodiments, the delay of the delay chain varies by a discrete time period in response to a change in logic states of the digital signals, and the maximum phase error between a phase of the reference clock signal and a phase of the feedback clock signal is less than the discrete time period when the digitally controlled delay-locked loop is in a lock mode.

Memory Interface Circuitry With Improved Timing Margins

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US Patent:
20140145756, May 29, 2014
Filed:
Nov 27, 2012
Appl. No.:
13/686727
Inventors:
Altera Corporation - , US
Warren Nordyke - Cupertino CA, US
Sean Shau-Tu Lu - San Jose CA, US
Ee Mei Ooi - Bayan Lepas, MY
Khai Nguyen - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/10
H03K 19/177
US Classification:
326 40, 36518905
Abstract:
Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller.
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Sean Lu from Foster City, CA Get Report