Sang H Kim

20070163838, Jul 19, 2007

Dec 5, 2006

11/566946

Sang Jin KIM - Renton WA, US

Advanced Ladders - Kent WA

E06C 1/00

1821784, 1821782

A modular ladder system is provided, wherein segments may be joined without limit to form a ladder of any desired length.

20100025154, Feb 4, 2010

Oct 9, 2009

12/576651

Sang Jin Kim - Renton WA, US

Advanced Ladders - Kent WA

E06C 1/38

1821784, 1821782

A modular ladder system is provided, wherein segments may be joined without limit to form a ladder of any desired length.

48599387, Aug 22, 1989

Jul 27, 1987

7/078094

Sang U. Kim - Tempe AZ
Mohammad K. Khan - Iselin NJ

Intel Corporation - Santa Clara CA

G01R 2726
G01R 3100

324158D

A novel technique to detect oxydonor generation in semiconductor wafers. Oxydonor generation in a P-type substrate may be sufficient to create a P-N junction within the substrate which may adversely affect device performance. A technique of the present invention is a two-step process for determining the presence of such an oxydonor generated P-N junction. For a capacitor device, the capacitance of the device is measured under varying test voltages to determine a capacitance-voltage response. Then a second capacitance-voltage response is measured when the device is subjected to an external energy source. For a diode device, the forward current is measured with the device under varying test voltages to determine a current-voltage response. Then a second currrent-voltage response is measured when the device is subjected to an external energy source. By comparing device response with and without the application of external energy, a device having oxydonor generation problems is efficiently detected.

48354589, May 30, 1989

Nov 9, 1987

7/118256

Sang U. Kim - Tempe AZ

Intel Corporation - Santa Clara CA

G01R 1512
G11C 1140
G06F 1126

324 73R

An error testing process for the testing of CMOS static RAM memories. Individual static RAM memory cells that have failed are isolated. A typical cell has six transistors, two access, two n-channel and two p-channel. The access transistors are allowed to float which effectively isolates the cell. By application of voltages to the n-channel or p-channel transistors one set can be turned off and the remaining two n-channel or p-channel transistors can be tested with microprobes varying voltages for the forward and reverse bias testing. The graphs of the current flow from these tests are compared using the signature analysis technique so that not only the exact transistor which failed can be identified but the failure mechanism can also be identified. This process permits error testing without damage to the RAM memory and without physical isolation of the SRAM memory.

20210326144, Oct 21, 2021

Jun 25, 2021

17/359392

- Santa Clara CA, US
Deepak Mathaikutty - Chandler AZ, US
Debabrata Mohapatra - Santa Clara CA, US
Sang Kyun Kim - San Jose CA, US
Gautham Chinya - Sunnyvale CA, US
Cormac Brick - San Francisco CA, US

G06F 9/445
G06F 9/50
G06F 9/30
G06N 20/00
H03K 19/177
H03K 19/20

Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.

20200012492, Jan 9, 2020

Sep 10, 2019

16/566355

- Redmond WA, US
Reuben R. Olinsky - Seattle WA, US
Sang Eun Kim - Bellevue WA, US
Edmund B. Nightingale - Bellevue WA, US
Thales de Carvalho - Issaquah WA, US

G06F 8/658
G06F 8/65
G06F 21/50
H04L 29/08
G06F 21/74

The disclosed technology is generally directed to updating of applications, firmware and/or other software on IoT devices. In one example of the technology, a request that is associated with a requested update is communicated from a normal world of a first application processor to a secure world of the first application processor. The secure world validates the requested update. Instructions associated with the validated update are communicated from the secure world to the normal world. Image requests are sent from the normal world to a cloud service for image binaries associated with the validated update. The secure world receives the requested image binaries from the cloud service. The secure world writes the received image binaries to memory, and validates the written image binaries.

20180165088, Jun 14, 2018

Feb 27, 2017

15/444024

- Redmond WA, US
Reuben R. Olinsky - Seattle WA, US
Sang Eun Kim - Bellevue WA, US
Edmund B. Nightingale - Bellevue WA, US
Thales de Carvalho - Issaquah WA, US

G06F 9/44
H04L 29/08

The disclosed technology is generally directed to updating of applications, firmware and/or other software on IoT devices. In one example of the technology, a request that is associated with a requested update is communicated from a normal world of a first application processor to a secure world of the first application processor. The secure world validates the requested update. Instructions associated with the validated update are communicated from the secure world to the normal world. Image requests are sent from the normal world to a cloud service for image binaries associated with the validated update. The secure world receives the requested image binaries from the cloud service. The secure world writes the received image binaries to memory, and validates the written image binaries.

20170263750, Sep 14, 2017

May 26, 2017

15/607054

Sang U. Kim - Chandler AZ, US
Kuhwan Kim - Chandler AZ, US

H01L 29/78
H01L 29/786
H01L 29/06
H01L 29/66

A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.