John Lau

58250840, Oct 20, 1998

Feb 11, 1997

8/795478

John H. Lau - Palo Alto CA
Yung Shih Chen - San Jose CA
Tai-Yu Chou - Pleasanto CA
Frank H. Wu - Sunnyvale CA
Kuan Luen Chen - San Jose CA
Wei H. Koh - Irvine CA

Express Packaging Systems, Inc. - Palo Alto CA

H01L 2312
H01L 2350
H01L 2328

257700

The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections. In addition to the benefits of high performance, low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.

60576014, May 2, 2000

Nov 27, 1998

9/200691

John H. Lau - Palo Alto CA
Tzyy Jang Tseng - Hsinchu, TW
Chen-Hua Cheng - Taoyuan Hsien, TW

Express Packaging Systems, Inc. - Palo Alto CA

H01L 2348

257738

The present invention discloses a new semiconductor ball grid array package for integrated circuits which have input and output counts higher than 250. The speed and performance characteristics of the semiconductor device contained in the package assembly are optimized while the packaging structure is simplified by utilizing only one dielectric layer and regular printed circuit board fabrication process. The complexities and higher cost for production of a multiple layer substrate for high-density interconnection configuration are thus resolved. The improved package assembly is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide interlayer connections. The package assembly applies a cavity down configuration with an integrated heat spreader attached.

60757108, Jun 13, 2000

Feb 11, 1999

9/248875

John H. Lau - Palo Alto CA

Express Packaging Systems, Inc. - Palo Alto CA

H05K 118

361760

The present invention discloses a novel electronic package. This semiconductor packaging assembly is for supporting and containing an integrated circuit (IC) chip. The IC chip is supported on a single core double-layer substrate as a flip chip which is solder-bumped with low melting point solder, e. g. , a 63 wt % Sn-37 wt % Pb eutectic solder. The flip chip is supported on a single core double-sided FR-4/5 or BT substrate provided with via holes to form via connections interconnecting the solder bumps to a land grid array disposed on the bottom surface of the substrate. The substrate is then surface mounted and soldered onto a printed circuit board which again is provided with low temperature 63 wt % Sn-37 wt % Pb eutectic solder paste for securely attaching the LGA CSP. Simplified processes are employed to assemble the electronic package with high yield processing steps, which can be conveniently carried out. CSP package with high reliability and improved performance characteristics can be achieved with a reduced production cost.

62990586, Oct 9, 2001

Apr 30, 1999

9/302695

John H. Lau - Palo Alto CA
Scott Lin - Fremont CA
Ming-Lun Szu - Taipei, TW

Hon Hai Precision Ind. Co., Ltd. - Taipei Hsien

B23K 3102

2282481

A method for positioning a solder ball onto a contact tail of an electrical connector comprises several steps. Firstly, arrange the contact tail into a center region and a peripheral region surrounding the center region. Secondly, attach solder paste onto the center region of the contact tail via a first mesh painting procedure. Thirdly, attach solder resist onto the peripheral region of the contact tail via a second mesh painting procedure. Fourthly, position a solder ball on the center region of the contact tail via a screen board. Fifthly, apply a reflow soldering procedure on the solder ball so that the solder ball can be soldered on the solder paste attached to the center region of the contact tail.