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Siu Sai Cheung

from San Ramon, CA
Age ~80
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Also known as:
Siu S Cheung, Sai Siu Cheung, Sai Cheung Siu, Kee Tang Siu, Siu Tang
Related to:
Yen Fong Tang, 63Louisa L Tang, 57Siu K Chan, 82Hoiyee CheungRobert Chio, 46Cheung Suk Chun, 77Winnie W Cheung, 49Cheungyee Yee Hedy, 46Jeffrey E Tang, 32Simon L Tang, 61Wing K Cheung, 76Ching C Choi, 79Ing K CheungChi C Cheung, 51Kee Tang Siu, 84Anthony K Cheung, 51Anna B Chio, 68
Connected to:
Adeline Cheung, 35Allen C Cheung, 48Angelica L Cheung, 32Anita J Cheung, 61Ava C Cheung, 57Barbara H Cheung, 76Beata Y Cheung, 46Benny Cheung, 51Catherine K Cheung, 43Cedric P Cheung, 50

Siu Cheung Phones & Addresses

  • San Ramon, CA
  • 801 Franklin St APT 1223, Oakland, CA 94607 (510) 451-1981
  • San Leandro, CA
  • Hayward, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Siu Yin Cheung
President
SMILING FACE INC
Dentist's Office
1610 Maxine Ave, San Mateo, CA 94401
Siu Ping Cheung
Manager
US Real Estate Opportunity Fund LLC
Siu Ping Cheung
Manager
Blue Crystals LLC
Siu Ping Cheung
Manager
Usre Asset LLC
Siu Ling Cheung
Northwest Heritage San Francisco LLC
Real Estate Investment · Real Estate Investments · Business Services at Non-Commercial Site · Nonclassifiable Establishments
6780 Lazy Riv Way, San Jose, CA 95120
1567 24 Ave, San Francisco, CA 94122

Publications

Us Patents

Optical Assembly With A Vertical Cavity Surface Emitting Laser Device Disposed On An Integrated Circuit Driver Chip

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US Patent:
20220407289, Dec 22, 2022
Filed:
Sep 15, 2021
Appl. No.:
17/447780
Inventors:
- San Jose CA, US
Hao HUANG - San Jose CA, US
Lijun ZHU - Dublin CA, US
Siu Kwan CHEUNG - San Jose CA, US
Kevin WANG - Fremont CA, US
John Michael MILLER - Ottawa, CA
International Classification:
H01S 5/026
H01S 5/0225
H01S 5/0233
Abstract:
An optical assembly includes a substrate; an optical subassembly that is disposed on a region of a surface of the substrate; a housing that is disposed on another region of the surface of the substrate; a first optical element that is disposed on a first support component of the housing; and a second optical element that is disposed on a second support component of the housing. The optical subassembly includes an integrated circuit (IC) driver chip; a redistribution layer (RDL) structure that is disposed on a surface of the IC driver chip, wherein the RDL structure includes a cavity; and a vertical cavity surface emitting laser (VCSEL) device disposed on a region of the surface of the RDL structure that is within the cavity of the RDL structure.

Packaging Substrate With Low Thermal Resistance And Low Parasitic Inductance

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US Patent:
20220385033, Dec 1, 2022
Filed:
Aug 24, 2021
Appl. No.:
17/445786
Inventors:
- San Jose CA, US
Hao HUANG - San Jose CA, US
Siu Kwan CHEUNG - San Jose CA, US
Huanlin ZHU - San Jose CA, US
Lijun ZHU - Dublin CA, US
International Classification:
H01S 5/024
H01L 23/373
H01L 23/498
H01S 5/02315
Abstract:
A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.

Substrate Designs For Time-Of-Flight Camera Projectors With Low Thermal Resistance And Low Parasitic Inductance

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US Patent:
20220385039, Dec 1, 2022
Filed:
Aug 24, 2021
Appl. No.:
17/445787
Inventors:
- San Jose CA, US
Hao HUANG - San Jose CA, US
Siu Kwan CHEUNG - San Jose CA, US
Huanlin ZHU - San Jose CA, US
Lijun ZHU - Dublin CA, US
International Classification:
H01S 5/183
G01S 7/4865
G01S 17/894
H01S 5/028
Abstract:
A circuit (e.g., for use in a time-of-flight camera projector module) may include a top metal layer having an anode and a cathode, one or more capacitors connected to the anode, a vertical-cavity surface-emitting laser connected to the anode and the cathode, and a driver connected to the cathode. The circuit may further include a bottom metal layer connected to ground and arranged below the top metal layer, and a dielectric layer separating the top metal layer and the bottom metal layer. In some implementations, the dielectric layer has a thickness under sixty micrometers and a thermal resistance under fifteen degrees Celsius per watt. Accordingly, a current loop flowing vertically across the dielectric layer has a low self-inductance based on the thickness of the dielectric layer and the bottom metal layer is arranged to dissipate heat generated by the current loop flowing vertically across the dielectric layer.

Driver Circuit For An Addressable Array Of Optical Emitters

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US Patent:
20220299610, Sep 22, 2022
Filed:
Jun 14, 2021
Appl. No.:
17/304070
Inventors:
- San Jose CA, US
Lijun ZHU - Dublin CA, US
Hao HUANG - San Jose CA, US
Siu Kwan CHEUNG - San Jose CA, US
International Classification:
G01S 7/4865
G01S 17/10
G01S 7/484
G01S 17/89
Abstract:
In some implementations, a driver circuit may include a source to provide an electrical input, and an array of optical emitters arranged in one or more rows and one or more columns. The array may include an optical emitter associated with a row and a column. The driver circuit may include a first switch having an open state and a closed state, and an inductive element connected to the row. The first switch in the closed state may cause current to charge the inductive element. The driver circuit may include a second switch having an open state and a closed state. The second switch in the closed state may select the column. The first switch transitioning from the closed state to the open state may cause the inductive element to discharge current through the row, and through the column when the second switch is in the closed state.

Optical Assembly That Includes An Optical Element Connected To A Vertical Cavity Surface Emitting Laser Device Via Two Or More Attachment Structures

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US Patent:
20230115690, Apr 13, 2023
Filed:
Dec 16, 2021
Appl. No.:
17/644679
Inventors:
- San Jose CA, US
Kevin WANG - Fremont CA, US
Hao HUANG - San Jose CA, US
John Michael MILLER - Ottawa, CA
Siu Kwan CHEUNG - San Jose CA, US
Lijun ZHU - Pleasanton CA, US
International Classification:
H01S 5/42
H01S 5/042
H01S 5/183
H01S 5/026
Abstract:
An optical assembly includes an integrated circuit (IC) driver chip; an optical subassembly disposed on the IC driver chip that includes: a vertical cavity surface emitting laser (VCSEL) device, an optical element disposed above a top surface of the VCSEL device, and two or more attachment structures disposed between the VCSEL device and the optical element; and two or more additional attachment structures disposed between the IC driver chip and the optical subassembly. The VCSEL device includes: a cathode contact disposed on the top surface of the VCSEL device, and an anode contact disposed on the top surface of the VCSEL device. The optical element includes two or more conductive traces on a bottom surface of the optical element. The two or more attachment structures are disposed between the two or more conductive traces of the optical element, and the cathode contact and the anode contact of the VCSEL device.

Optical Assembly With A Microlens Component And Contacts On A Same Surface Of A Vertical Cavity Surface Emitting Laser Device

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US Patent:
20230027279, Jan 26, 2023
Filed:
Sep 29, 2021
Appl. No.:
17/449386
Inventors:
- San Jose CA, US
Kevin WANG - Fremont CA, US
Hao HUANG - San Jose CA, US
John Michael MILLER - Ottawa, Ontario, CA
Siu Kwan CHEUNG - San Jose CA, US
Lijun ZHU - Pleasanton CA, US
International Classification:
H01S 5/183
H01S 5/42
H01S 5/024
H01S 5/026
Abstract:
In some implementations, an optical assembly includes a substrate that includes a thermally conductive core, an IC driver chip that is disposed on a first surface of the substrate, and a VCSEL device that includes an electrically insulated surface that is disposed on the thermally conductive core of the substrate within a cavity formed in the second surface of the substrate. The VCSEL device includes a cathode contact disposed on a surface of the VCSEL device and an anode contact disposed on the surface of the VCSEL device. The VCSEL device includes a plurality of emitters and a microlens component that is disposed over the plurality of emitters on the surface of the VCSEL device.

Wafer Prober To Facilitate Testing Of A Wafer Using Nanosecond Pulses

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US Patent:
20210325451, Oct 21, 2021
Filed:
Jun 30, 2020
Appl. No.:
16/917124
Inventors:
- San Jose CA, US
Lucas MORALES - San Francisco CA, US
Raman SRINIVASAN - Fremont CA, US
Sean BURNS - Menlo Park CA, US
Siu Kwan CHEUNG - San Jose CA, US
Tian SHI - Fremont CA, US
Tao LI - Fremont CA, US
International Classification:
G01R 31/28
Abstract:
A wafer testing system may comprise a chuck, a wafer carrier, a cathode plate, and a probe card. The chuck may be configured to hold the wafer carrier. The wafer carrier may be configured to hold a wafer on a surface of the wafer carrier, wherein the surface of the wafer carrier comprises one or more contact features protruding from the surface of the wafer carrier. The cathode plate may be configured to provide an electrical connection between the wafer carrier and the probe card, wherein a portion of a surface of the cathode plate is configured to be disposed on the one or more contact features of the wafer carrier. The probe card may be configured to test, using one or more probes associated with the probe card, the wafer when the wafer is on the surface of the wafer carrier.

Optical Modulator

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US Patent:
20180173026, Jun 21, 2018
Filed:
Oct 27, 2017
Appl. No.:
15/796170
Inventors:
- Milpitas CA, US
Siu Kwan CHEUNG - San Jose CA, US
David M. SHEMO - Avon CT, US
David GLASSNER - Morgan Hill CA, US
Ed L. WOOTEN - San Jose CA, US
International Classification:
G02F 1/03
G02F 1/035
Abstract:
An optical modulator may include at least one ground electrode. The optical modulator may include at least one signal electrode parallel to the at least one ground electrode. The optical modulator may include at least one waveguide parallel to the at least one ground electrode and the at least one signal electrode. The optical modulator may include a first substrate disposed underneath the at least one ground electrode and the at least one signal electrode relative to a surface of the optical modulator. The optical modulator may include a second substrate disposed underneath at least a portion of the first substrate relative to the surface of the optical modulator. The optical modulator may include a floating conductor disposed between the first substrate and the second substrate.
Control profile
Siu Sai Cheung from San Ramon, CA, age ~80 Get Report