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Qing X Liu

from Rosemead, CA
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Related to:
Biao Liu, 38Min LiuXu X XiaShuo Liu, 37Sabrina Yu, 51Wei Wilson, 78Weishan Liu, 62Wen Liu Bi, 66Changhai Liu, 39Wei Liu, 64
Connected to:
Adela Liu, 73Alec X Liu, 39Alpha T Liu, 46Amon Y Liu, 58Andrea Y Liu, 46Anqi Liu, 39Arden K Liu, 64Ba S Liu, 62Bailu Liu, 35Ban Liu, 48

Qing Liu Phones & Addresses

  • Rosemead, CA
  • Monterey Park, CA
  • Modesto, CA

Professional Records

License Records

Qing Mei Liu

License #:
PTC.021858 - Expired
Issued Date:
Sep 10, 2014
Expiration Date:
Mar 10, 2016
Type:
Pharmacy Technician Candidate

Qing An Liu

License #:
FMC03892 - Expired
Category:
Food Safety
Issued Date:
Apr 26, 1996
Expiration Date:
Jan 31, 1999
Type:
Certified Food Safety Mgr

Medicine Doctors

Qing Liu Photo 1

Qing Liu

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Specialties:
Internal Medicine
Work:
IPC Healthcare
111 Continental Dr STE 406, Newark, DE 19713
(302) 368-2630 (phone), (302) 368-1271 (fax)
Education:
Medical School
University of Illinois, Chicago College of Medicine
Graduated: 2000
Languages:
English
Description:
Dr. Liu graduated from the University of Illinois, Chicago College of Medicine in 2000. He works in Newark, DE and specializes in Internal Medicine. Dr. Liu is affiliated with Christiana Hospital, Saint Francis Healthcare and Wilmington Hospital.
Qing Liu Photo 2

Qing Liu

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Specialties:
Anesthesiology
Work:
East Manhattan Anesthesia Partners
310 E 14 St, New York, NY 10003
(212) 979-4464 (phone), (212) 614-8233 (fax)
Education:
Medical School
Cornell University Weill Medical College
Graduated: 2001
Languages:
Chinese
English
Russian
Spanish
Description:
Dr. Liu graduated from the Cornell University Weill Medical College in 2001. She works in New York, NY and specializes in Anesthesiology. Dr. Liu is affiliated with New York Eye & Ear Infirmary Of Mount Sinai.
Qing Liu Photo 3

Qing Yan Liu

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Qing Liu Photo 4

Qing Liu

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Specialties:
Internal Medicine
Hospitalist
Education:
Shanghai First Medical College (1988)

Resumes

Resumes

Qing Liu Photo 5

Qing Liu Farmingdale, NY

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Work:
Self-Employed
Apr 2011 to Present
Bank of China
New York, NY
Apr 2010 to Apr 2011
Temporary Clerk, Compliance, New Accounts
Bank of China
Qingdao, CN
Jun 2009 to Aug 2009
Risk Management Assistant/Intern
Insurance Services
Monterey Park, CA
Jun 2007 to Aug 2007
Office Assistant
Recursion Software, Inc
Frisco, TX
Sep 2003 to Dec 2003
Associate Programmer/Intern
Education:
Claremont Graduate University
Claremont, CA
2010
M.S. in Financial Engineering
University of Texas at Dallas
Richardson, TX
2004
B.S. in Computer Science
Skills:
Microsoft Office, Word, Excel, Powerpoint, HTML, C/C++, Crystal Report

Business Records

Name / Title
Company / Classification
Phones & Addresses
Qing Liu
President
Tql Trading Inc
Whol Nondurable Goods
3060 W Vly Blvd, Alhambra, CA 91803
349 S Los Angeles St, Los Angeles, CA 90013
(213) 687-0228
Qing Liu
Dreamland Investments, LLC
13980 Central Ave, Chino, CA 91710
Qing Xian Liu
Songda Investments LLC
Investor
6361 Sultana Ave, San Gabriel, CA 91775
Qing Liu
President, Principal
A Computer Electronics Supplie
Whol Durable Goods
584 W 22 St, Upland, CA 91784
Qing Liu
President
L & L PACIFIC INTERNATIONAL INC
Nonclassifiable Establishments
15350 Fairfield Rnch Rd Unite #E, Chino Hills, CA 91709
1300 John Reed Ct, Whittier, CA 91745
14020 Central Ave, Chino, CA 91710
5595 Daniels St, Chino, CA 91710
(909) 902-9259
Qing Liu
President
Darunfar Marble Corp
Whol Brick/Stone Material · Nonclassifiable Establishments
8861 Katella Ave, Anaheim, CA 92804
2100 E Howell Ave, Anaheim, CA 92806
15197 Avenida Rorras, San Diego, CA 92128
1548 W Collins Ave, Orange, CA 92867
Qing Liu
OHIO CENTER FOR EAST-WEST CULTURAL EXCHANGE
Qing Liu
President
Ging Arts Inc
7434 Mooney Dr, Rosemead, CA 91770

Publications

Isbn (Books And Publications)

Algebraic Geometry and Arithmetic Curves

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Author

Qing Liu

ISBN #

0198502842

Algebraic Geometry And Arithmetic Curves

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Author

Qing Liu

ISBN #

0199202494

Rough Sets, Fuzzy Sets, Data Mining, and Granular Computing: 9th International Conference, Rsfdgrc 2003, Chongqing, China, May 26-29, 2003 Proceedings

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Author

Qing Liu

ISBN #

3540140409

Us Patents

Fin-Based Field Effect Transistor (Finfet) Device With Enhanced On-Resistance And Breakdown Voltage

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US Patent:
20230088066, Mar 23, 2023
Filed:
Sep 21, 2021
Appl. No.:
17/481204
Inventors:
- Singapore, SG
Qing LIU - irvine CA, US
International Classification:
H01L 27/088
H01L 29/78
H01L 29/08
H01L 29/66
H01L 21/8234
Abstract:
A fin-based field effect transistor (finFET) device may include a fin structure having a first portion, a second portion and a third portion. The finFET device may include a first gate structure disposed over at least part of the first portion, a first source/drain region disposed in the first portion, and a second drain/source region disposed in the third portion. Each of the first, second and third portions may include one or more fin portions. The total fin count in the second portion is fewer than the total fin count in the first portion. The second portion may include a drift region. Methods of fabricating a finFET are also disclosed. The finFET device provides a lower on-resistance and a higher breakdown voltage than conventional finFETs.

Lateral Double-Diffused Metal-Oxide-Semiconductor (Ldmos) Fin Field Effect Transistor With Enhanced Capabilities

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US Patent:
20210135006, May 6, 2021
Filed:
Oct 30, 2019
Appl. No.:
16/669193
Inventors:
- Singapore, SG
Qing Liu - Irvine CA, US
Assignee:
Avago Technologies International Sales Pte. Ltd. - Singapore
International Classification:
H01L 29/78
H01L 29/66
H01L 29/06
Abstract:
A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a first surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the first surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the first surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

Folded Channel Vertical Transistor And Method Of Fabricating Same

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US Patent:
20210036151, Feb 4, 2021
Filed:
Jul 29, 2019
Appl. No.:
16/525015
Inventors:
- Singapore, SG
Qing Liu - Irvine CA, US
International Classification:
H01L 29/78
H01L 29/66
H01L 21/762
Abstract:
A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures.

Bi-Directional Transistor Devices

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US Patent:
20200111780, Apr 9, 2020
Filed:
Oct 9, 2018
Appl. No.:
16/155551
Inventors:
- Singapore, SG
Qing Liu - Irvine CA, US
International Classification:
H01L 27/088
H01L 27/02
Abstract:
A transistor device includes a substrate a first transistor structure. The first transistor structure includes a first fin structure on the substrate. The first fin structure includes a first doped region, and a second fin structure on the substrate spaced apart from the first fin structure. The second fin structure includes a second doped region and a third doped region spaced apart from the second doped region. The transistor device includes a first electrode on the second fin structure and covering a first end of the second fin structure.

Depleted Fin Transistor And Method Of Fabricating

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US Patent:
20200098914, Mar 26, 2020
Filed:
Sep 20, 2018
Appl. No.:
16/137148
Inventors:
- Singapore, SG
Qing Liu - Irvine CA, US
Assignee:
Avago Technologies International Sales Pte. Limited. - Singapore
International Classification:
H01L 29/78
H01L 27/12
H01L 29/06
H01L 29/66
H01L 21/84
Abstract:
A transistor includes at least one fin structure (e.g., three fin structures) and a gate. The fin structure is disposed above a semiconductor layer above an insulator layer of a semiconductor on insulator substrate. The gate is disposed over at least three sides of the fin structure and a portion of the semiconductor layer. A channel for the transistor is disposed in fin structure and the portion under the gate.

Method Of Making A Vertical Pillar Device And Structure Thereof

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US Patent:
20200052128, Feb 13, 2020
Filed:
Aug 7, 2018
Appl. No.:
16/057612
Inventors:
- Singapore, SG
Qing Liu - Irvine CA, US
International Classification:
H01L 29/786
H01L 29/66
H01L 29/423
H01L 29/20
H01L 29/16
Abstract:
A vertical pillar device includes a substrate, one or more pillars, a drain section, and a source section. The one or more pillars include a first end and a second end. The first end is connected to the substrate at a first interface. The substrate and the one or more pillars are made of different materials. The drain section surrounds the one or more pillars near the first end and away from the first interface. The source section connects to the one or more pillars at the second end.

Methods And Systems Of Realizing Multiple Gate Length In Transistor

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US Patent:
20200044094, Feb 6, 2020
Filed:
Aug 1, 2018
Appl. No.:
16/052138
Inventors:
- Singapore, SG
Qing Liu - Irvine CA, US
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:
H01L 29/786
H01L 27/088
H01L 29/10
H01L 21/223
H01L 21/28
H01L 21/8234
Abstract:
A method of fabricating a semiconductor structure includes forming a plurality of Fin structures, doping first dopants at both sides of a first Fin structure of the Fin structures, and providing a first thermal diffusion operation to the semiconductor structure. The method also includes doping second dopants at both sides of a second Fin structure of the Fin structures, and providing a second thermal diffusion operation to the semiconductor structure. A first gate length for the first Fin structure is formed using the first and the second thermal diffusion operations, and a second gate length for the second Fin structure using the second thermal diffusion operation. The first dopants are of the same type or a different type.

Fin Profile For Bulk Based Silicon-On-Insulation Finfet Device

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US Patent:
20190131445, May 2, 2019
Filed:
Oct 30, 2017
Appl. No.:
15/798291
Inventors:
- Singapore, SG
Qing LIU - Irvine CA, US
International Classification:
H01L 29/78
H01L 29/06
H01L 29/66
H01L 21/308
H01L 21/762
H01L 21/02
Abstract:
A semiconductor device includes a substrate, and a semiconductor fin structure formed on the substrate. The semiconductor device also includes a dielectric liner disposed on and in direct contact with a top surface of the substrate and a sidewall of the semiconductor fin structure. The semiconductor device includes a first isolation layer disposed on and in direct contact with a top surface and a sidewall of the dielectric liner. The semiconductor device also includes a second isolation layer disposed on and in direct contact with a top surface of the first isolation layer and a sidewall of the semiconductor fin structure. The semiconductor device also includes an oxide isolation region formed beneath the semiconductor fin structure by oxidation through the second isolation layer.
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Qing X Liu from Rosemead, CA Get Report