Qi Wang

6728945, Apr 27, 2004

Feb 26, 2001

09/793309

Qi Wang - San Jose CA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 18, 716716, 716 17

A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.

7007247, Feb 28, 2006

May 24, 2002

10/155323

Qi Wang - San Jose CA, US
Sumit Roy - Milpitas CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716 2, 716 3, 716 7, 716 6, 716 18

The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.

7276372, Oct 2, 2007

Dec 19, 2003

10/741657

Debbie Law - San Francisco CA, US
Qi Wang - San Francisco CA, US
Robert DuBridge - Belmont CA, US
Vinay Bhaskar - San Francisco CA, US

PDL Biopharma, Inc. - Fremont CA

C12N 5/20

435330, 5303871, 5303873, 5303877, 5303879, 5303888, 5303913, 5303917, 435331, 435344

GPR64 antibody compositions are provided. These antibodies may be used for diagnosis or treatment of cancer, especially ovarian cancer, Ewing's sarcoma, uterine cancer, and other GPR64 expressing tumor types.

7280879, Oct 9, 2007

May 20, 2004

10/850686

Martin Chen - Los Gatos CA, US
Shailesh P. Mane - San Jose CA, US
Gaurav Sharma - San Jose CA, US
Qi Wang - Cupertino CA, US
Dallan Clancy - Belmont CA, US
Mario Günter Rothenburg - Eppelheim, DE
Uwe Kohler - Dielheim, DE

SAP AG - Walldorf

G06F 19/00
G06F 9/45
G06F 17/50
G05B 13/02
G06F 7/60

700 97, 700 42, 703 22, 703 16

A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store a time dependent process parameter related to the production process, having uploaded them via an interface. The time dependent process parameters may be retrieve and displayed to the user on a display using a remote function call enabled function module. The time dependent process parameters may be uploaded from an external system or revised using a remote function call enabled function module.

7530047, May 5, 2009

Jun 5, 2006

11/447683

Qi Wang - San Jose CA, US
Ranganathan Sankaralingam - Noida, IN

Cadence Design Systems, Inc. - San Jose CA

G06F 17/50

716 18, 716 17, 716 3

A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.

7571078, Aug 4, 2009

May 20, 2004

10/851361

Martin Chen - Los Gatos CA, US
Shailesh P. Mane - San Jose CA, US
Gaurav Sharma - San Jose CA, US
Qi Wang - Cupertino CA, US
Dallan Clancy - Belmont CA, US
Mario Günter Rothenburg - Eppelheim, DE
Uwe Kohler - Dielheim, DE

SAP AG - Walldorf

G06F 17/10

703 2

A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store a time dependent process parameter related to the specific product design and organize the time dependent process parameters by product variants. The time dependent process parameter may have a parameter value and a start time. The time dependent process parameters may be input/output component consumption parameters, activity duration parameters, resource capacity consumption parameters, and activity scrap parameters.

7603262, Oct 13, 2009

May 20, 2004

10/850796

Martin Chen - Los Gatos CA, US
Shailesh P. Mane - San Jose CA, US
Gaurav Sharma - San Jose CA, US
Qi Wang - Cupertino CA, US
Dallan Clancy - Belmont CA, US
Mario Günter Rothenburg - Eppelheim, DE
Uwe Kohler - Dielheim, DE

SAP AG - Walldorf

G06G 7/48
G06G 7/75
G06G 7/00
G06F 15/00
G06F 19/00
G06F 17/00
G06F 9/46
G06F 17/50
A01K 5/02

703 6, 700 95, 700 96, 700 97, 700 98, 700102, 705 9, 705 29

A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store one or more time dependent process parameters related to the production process and one or more engineering change numbers related to different product designs. The effective time periods of the time dependent process parameters may be compared with the effective time periods of the engineering change numbers. Various flags may be associated with each comparison to indicate the validity of the time dependent process parameter.

7635635, Dec 22, 2009

Apr 6, 2006

11/400731

Hamza Yilmaz - Saratoga CA, US
Qi Wang - Sandy UT, US
Minhua Li - Sandy UT, US
Chung-Lin Wu - San Jose CA, US

Fairchild Semiconductor Corporation - South Portland ME

H01L 21/46

438455, 438406, 438464, 257E21088, 257E2151

A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.