Qi Wang from Mountain View, CA

Professional Records

Lawyers & Attorneys

Qi Wang - Lawyer

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ISLN:

1000267626

Admitted:

2017

Medicine Doctors

Qi Wang

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Specialties:

Anatomic Pathology & Clinical Pathology

Work:

St Peters University Hospital Pathology
254 Easton Ave FL 5, New Brunswick, NJ 08901
(732) 745-8534 (phone), (732) 220-8595 (fax)

Education:

Medical School
Beijing Med Univ, Beijing City, Beijing, China
Graduated: 1986

Languages:

English

Description:

Dr. Wang graduated from the Beijing Med Univ, Beijing City, Beijing, China in 1986. She works in New Brunswick, NJ and specializes in Anatomic Pathology & Clinical Pathology. Dr. Wang is affiliated with Saint Peters University Hospital.

Qi Wang

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Business Records

Name / Title

Company / Classification

Phones & Addresses

Qi Wang
Manager

Cadence Design Systems Inc
Prepackaged Software

555 River Oaks Pkwy Bldg 1, San Jose, CA 95134

Qi Wang
Manager

Cadence Design Systems Inc
Prepackaged Software

555 River Oaks Pkwy Bldg 1, San Jose, CA 95134

Qi Wang
President

Primemed, Inc

311 N Verdugo Rd, Glendale, CA 91206

Qi Wang
President

Mars Trucking Inc

608 E Vly Blvd, San Gabriel, CA 91776

Qi Wang
President

Xin Yun Industrial, Inc

10430 S De Anza Blvd, Cupertino, CA 95014

Qi Wang
President

BUSINESS INTELLIGENCE MANAGEMENT CORPORATION

119 S Msn Dr, San Gabriel, CA 91776
713 W Duarte Rd, Arcadia, CA 91007

Qi Wang
President

PACGRAN INC
Nonclassifiable Establishments · Truck Terminal Facility

19300 S Alameda St, Compton, CA 90221
928 N San Fernando Blvd, Burbank, CA 91504
880 Sunset Pl, Pomona, CA 91765
771 E Watson Ctr Rd, Long Beach, CA 90745

Qi Wang
President

CHINA CONSONG IMPORT & EXPORT USA CO. LTD

16043 Clearbrook Ln, Cerritos, CA 90703

Qi Wang
President

KSS INTERNATIONAL, INC
Nonclassifiable Establishments

600 S Main St #959F, Orange, CA 92868
809 S Atlantic Blvd, Monterey Park, CA 91754

Publications

Us Patents

Behavioral Level Observability Analysis And Its Applications

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US Patent:

6728945, Apr 27, 2004

Filed:

Feb 26, 2001

Appl. No.:

09/793309

Inventors:

Qi Wang - San Jose CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 18, 716716, 716 17

Abstract:

A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.

Method And Mechanism For Rtl Power Optimization

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US Patent:

7007247, Feb 28, 2006

Filed:

May 24, 2002

Appl. No.:

10/155323

Inventors:

Qi Wang - San Jose CA, US
Sumit Roy - Milpitas CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 3, 716 7, 716 6, 716 18

Abstract:

The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.

Interfaces From External Systems To Time Dependent Process Parameters In Integrated Process And Product Engineering

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US Patent:

7280879, Oct 9, 2007

Filed:

May 20, 2004

Appl. No.:

10/850686

Inventors:

Martin Chen - Los Gatos CA, US
Shailesh P. Mane - San Jose CA, US
Gaurav Sharma - San Jose CA, US
Qi Wang - Cupertino CA, US
Dallan Clancy - Belmont CA, US
Mario Günter Rothenburg - Eppelheim, DE
Uwe Kohler - Dielheim, DE

Assignee:

SAP AG - Walldorf

International Classification:

G06F 19/00
G06F 9/45
G06F 17/50
G05B 13/02
G06F 7/60

US Classification:

700 97, 700 42, 703 22, 703 16

Abstract:

A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store a time dependent process parameter related to the production process, having uploaded them via an interface. The time dependent process parameters may be retrieve and displayed to the user on a display using a remote function call enabled function module. The time dependent process parameters may be uploaded from an external system or revised using a remote function call enabled function module.

Optimized Mapping Of An Integrated Circuit Design To Multiple Cell Libraries During A Single Synthesis Pass

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US Patent:

7530047, May 5, 2009

Filed:

Jun 5, 2006

Appl. No.:

11/447683

Inventors:

Qi Wang - San Jose CA, US
Ranganathan Sankaralingam - Noida, IN

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 17, 716 3

Abstract:

A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.

Time Dependent Process Parameters For Integrated Process And Product Engineering

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US Patent:

7571078, Aug 4, 2009

Filed:

May 20, 2004

Appl. No.:

10/851361

Inventors:

Assignee:

SAP AG - Walldorf

International Classification:

G06F 17/10

US Classification:

703 2

Abstract:

A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store a time dependent process parameter related to the specific product design and organize the time dependent process parameters by product variants. The time dependent process parameter may have a parameter value and a start time. The time dependent process parameters may be input/output component consumption parameters, activity duration parameters, resource capacity consumption parameters, and activity scrap parameters.

Time Dependent Process Parameters And Engineering Change Number Conflict Report

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US Patent:

7603262, Oct 13, 2009

Filed:

May 20, 2004

Appl. No.:

10/850796

Inventors:

Assignee:

SAP AG - Walldorf

International Classification:

G06G 7/48
G06G 7/75
G06G 7/00
G06F 15/00
G06F 19/00
G06F 17/00
G06F 9/46
G06F 17/50
A01K 5/02

US Classification:

703 6, 700 95, 700 96, 700 97, 700 98, 700102, 705 9, 705 29

Abstract:

A method and apparatus for computer modeling the production process is disclosed. An integrated product and process engineering system may be a computer modeling system that models both a generic production process and a specific individual production process. The integrated product and process engineering system may store one or more time dependent process parameters related to the production process and one or more engineering change numbers related to different product designs. The effective time periods of the time dependent process parameters may be compared with the effective time periods of the engineering change numbers. Various flags may be associated with each comparison to indicate the validity of the time dependent process parameter.

Method For Bonding A Semiconductor Substrate To A Metal Substrate

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US Patent:

7635635, Dec 22, 2009

Filed:

Apr 6, 2006

Appl. No.:

11/400731

Inventors:

Hamza Yilmaz - Saratoga CA, US
Qi Wang - Sandy UT, US
Minhua Li - Sandy UT, US
Chung-Lin Wu - San Jose CA, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/46

US Classification:

438455, 438406, 438464, 257E21088, 257E2151

Abstract:

A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.