Nhan Van Do

7851846, Dec 14, 2010

Dec 3, 2008

12/327114

Nhan Do - Saratoga CA, US
Hieu V. Tran - San Jose CA, US
Amitay Levi - Cupertino CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

H01L 29/788
H01L 21/28

257320, 257319, 257E293, 257E21179, 438257, 438267

A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a bottom wall of the trench, a second portion that extends along a sidewall of the trench, and a third portion that extends along the surface of the substrate. The floating gate is disposed over the channel region third portion. The control gate is disposed over the floating gate. The select gate is at least partially disposed in the trench and adjacent to the channel region first and second portions. The erase gate disposed adjacent to and insulated from the floating gate.

8148768, Apr 3, 2012

Nov 26, 2008

12/324816

Nhan Do - Saratoga CA, US
Amitay Levi - Cupertino CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

H01L 29/788

257315, 257204, 257316, 257E293, 257E21422, 438588

A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. The erase gate includes a notch, and the floating gate includes an edge that directly faces and is insulated from the notch.

8384147, Feb 26, 2013

Apr 29, 2011

13/097766

Nhan Do - Saratoga CA, US
Amitay Levi - Cupertino CA, US

Silicon Storage Technology, Inc. - San Jose CA

H01L 29/792
H01L 29/788
G11C 7/00

257315, 257321, 3651851

Systems of electrically programmable and erasable memory cell are disclosed. In one exemplary implementation, a cell may have two storage transistors in a substrate of semiconductor material of a first cooductivity type The first storage transistor is of the type having a first region and a second region each of a second conductivity type in the substrate The second storage transistor is of the type having a third region and a fourth region each of a second conductivity type in the substrate. Arrays formed of such memory cells and non-volatile memory cells are also disclosed.

8513728, Aug 20, 2013

Nov 17, 2011

13/299320

Parviz Ghazavi - San Jose CA, US
Hieu Van Tran - San Jose CA, US
Nhan Do - Saratoga CA, US

Silicon Storage Technology, Inc. - San Jose CA

H01L 29/788

257320, 257316, 257319, 257E293

An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.

20130121085, May 16, 2013

May 3, 2012

13/463558

Nhan Do - Saratoga CA, US
Elizabeth A. Cuevas - Los Gatos CA, US
Yuri Tkachev - Sunnyvale CA, US
Mandana Tadayoni - Cupertino CA, US

G11C 16/26

36518529, 36518518

A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

20130234223, Sep 12, 2013

Mar 7, 2012

13/414400

Willem-Jan Toren - St. Maximin, FR
Xian Liu - Sunnyvale CA, US
Gerhard Metzger-Brueckl - Geisenfeld, DE
Nhan Do - Saratoga CA, US
Stephan Wege - Bannewitz-Cunnersdorf, DE
Nadia Miridi - Auriol, FR
Chien-Sheng Su - Saratoga CA, US
Cecile Bernardi - Bouc Bel Air, FR
Liz Cuevas - Los Gatos CA, US
Florence Guyot - Venelles, FR
Yueh-Hsin Chen - Pleasanton CA, US
Mandana Tadayoni - Cupertino CA, US

H01L 27/088
H01L 21/762

257316, 438424, 257E293, 257E2706, 257E21546

A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

20130242672, Sep 19, 2013

Mar 13, 2012

13/419269

Hieu Van Tran - San Jose CA, US
Hung Quoc Nguyen - Fremont CA, US
Nhan Do - Saratoga CA, US

G11C 16/04

36518529

An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.

20140057422, Feb 27, 2014

Aug 23, 2012

13/593448

XIAN LIU - Sunnyvale CA, US
MANDANA TADAYONI - Cupertino CA, US
CHIEN-SHENG SU - Saratoga CA, US
NHAN DO - Saratoga CA, US

H01L 21/04

438510, 257E2104

A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.