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Ngoc Thi Minh Le

from Walnut, CA
Age ~38

Ngoc Le Phones & Addresses

  • Walnut, CA
  • 200 W Grand Ave APT F, Alhambra, CA 91801
  • Brea, CA
  • Glendale, AZ
  • Norwalk, CA
  • Fountain Valley, CA

Professional Records

License Records

Ngoc Anh Le

License #:
PST.019076 - Expired
Issued Date:
May 10, 2010
Expiration Date:
Dec 31, 2010
Type:
Pharmacist

Ngoc M. Le

License #:
MA.002163 - Active
Issued Date:
Jul 19, 2013
Expiration Date:
Mar 31, 2017
Type:
Medication Administration (V)

Ngoc M. Le

License #:
PIC.019711 - Active
Issued Date:
Jan 12, 2012
Expiration Date:
Dec 31, 2017
Type:
Pharmacist-in-Charge (V)

Ngoc M. Le

License #:
PST.019711 - Active
Issued Date:
Jan 12, 2012
Expiration Date:
Dec 31, 2017
Type:
Pharmacist

Ngoc T. Le

License #:
MA.000785 - Active
Issued Date:
Aug 12, 2010
Expiration Date:
Jan 5, 2018
Type:
Medication Administration (V)

Ngoc T. Le

License #:
PIC.019225 - Active
Issued Date:
Aug 24, 2010
Expiration Date:
Dec 31, 2017
Type:
Pharmacist-in-Charge (V)

Ngoc T. Le

License #:
PNT.045333 - Expired
Issued Date:
Jan 29, 2007
Expiration Date:
Aug 24, 2010
Type:
Pharmacy Intern

Ngoc T. Le

License #:
PST.019225 - Active
Issued Date:
Aug 24, 2010
Expiration Date:
Dec 31, 2017
Type:
Pharmacist

Medicine Doctors

Ngoc Le Photo 1

Ngoc H. Le

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Specialties:
Family Medicine
Work:
Augusta Medical GroupAugusta Health Family Practice Verona
1 Grn Hl Dr, Verona, VA 24482
(540) 245-7425 (phone), (540) 245-7430 (fax)
Education:
Medical School
New York College of Osteopathic Medicine of New York Institute of Technology
Graduated: 1994
Conditions:
Abnormal Vaginal Bleeding
Acne
Acute Bronchitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Languages:
English
Description:
Dr. Le graduated from the New York College of Osteopathic Medicine of New York Institute of Technology in 1994. She works in Verona, VA and specializes in Family Medicine. Dr. Le is affiliated with Augusta Health Care Inc.

Lawyers & Attorneys

Ngoc Le Photo 2

Ngoc Kim Le, Long Beach CA - Lawyer

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Address:
Marron Lawyers
320 Golden Shore Ste 410, Long Beach, CA 90802
(949) 679-9823 (Office), (949) 266-9181 (Fax)
Licenses:
California - Active 2011
Education:
University of California, Davis - School of Law
Degree - J.D.
Graduated - 2011
University of California - Los Angeles
Degree - B.A.
Graduated - 2007
UC Davis SOL King Hall
Specialties:
Litigation - 100%

Resumes

Resumes

Ngoc Le Photo 3

Ngoc Le Garden Grove, CA

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Work:
School of Continue Education
Cypress, CA
Jan 2013 to Sep 2013
Teacher's Assistant (TA)

Thien
Garden Grove, CA
Jan 2011 to Jan 2012
Lab Technician

Optisource Technologies Inc
Anaheim, CA
Sep 2007 to Sep 2009
Quality Control Technician

Education:
Program Design in Knes & Hs
Sep 2012 to 2000
Measurements/Statistics

California State University
Fullerton, CA
2015
Bachelor of Science in Health Science

Ngoc Le Photo 4

Ngoc Anh Le Garden Grove, CA

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Work:
Vietnamese Grace Church

Mar 2010 to 2000
VOLUNTEER CHURCH BOARD MEMBER- Coach

Little Saigon C.R.C. Tutor Center
Westminster, CA
Jun 2007 to Dec 2009
TUTOR

General Practice Office
Garden Grove, CA
Jul 2005 to Apr 2008
MEDICAL ASSISTANT FRONT OFFICE

Education:
University of the Rockies
2012 to 2014
Master of Psychology in Organizational Psychology

University of California
Riverside, CA
Sep 2005 to Mar 2007
Bachelor of Art in Sociology

Loara High School
Sep 1998 to Jun 2002
High School Diploma

Skills:
Communication, Computer, management, Couselor, Collaborator, Bahavioral Interventionist
Ngoc Le Photo 5

Ngoc Le Phoenix, AZ

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Work:
Visionary Bits LLC
Phoenix, AZ
Property Manager

Education:
Arizona State University
Tempe, AZ
Jan 2006 to Jan 2010
BS in Finance

Central High School
Phoenix, AZ
Jan 2002 to Jan 2006

Publications

Us Patents

Testing Memory Modules On A Solder-Side Adaptor Board Attached To A Pc Motherboard

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US Patent:
6357022, Mar 12, 2002
Filed:
Oct 11, 2000
Appl. No.:
09/686044
Inventors:
Thang Nguyen - Santa Ana CA
Ngoc Le - Mission Viejo CA
Benjamin E. Chou - Irvine CA
Assignee:
Kingston Technology Co. - Fountain Valley CA
International Classification:
H02H 305
US Classification:
714 42
Abstract:
Memory modules such as SIMMs and DIMMs are automatically tested by a target-system motherboard such as a PC motherboard. An automated SIMM/DIMM handler is connected to a handler adaptor board that is mounted to the back or solder-side of the PC motherboard. The relatively flat surface of the solder-side of the PC motherboard allows close mounting of the handler. One or more of the SIMM sockets on the motherboard is removed to provide mounting holes for the handler adaptor board. The handler adaptor board provides electrical connection from the module-under-test (MUT) in the handler to the removed SIMM socket on the PC motherboard. The handler adaptor board provides a slight spacing or offset from the solder-side surface of the PC motherboards substrate, allowing the handler to be plugged directly into tester-connectors on the handler adaptor board. Since the offset of the adaptor board is slight, the length of electrical connections to the handler is short, minimizing the load on the PCs memory bus. A handler controller card that controls the handler is plugged into the PCI or ISA bus on the PC motherboard.

Plasma Etch Process For Multilayer Vias Having An Organic Layer With Vertical Sidewalls

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US Patent:
7125796, Oct 24, 2006
Filed:
Nov 30, 2004
Appl. No.:
11/000832
Inventors:
Donald F. Weston - Phoenix AZ, US
William J. Dauksher - Mesa AZ, US
Ngoc V. Le - Gilbert AZ, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21/4763
H01L 21/461
US Classification:
438637, 257E21218, 257E21577, 257E21313, 257E216, 257E21024
Abstract:
A process is provided for fabricating a via between bonded wafers without undercutting an organic bonding material. The process for forming the via in a structure including a dielectric material and an organic bonding material , comprises forming a resist material on the dielectric layer and etching through the dielectric layer and the organic bonding material with 60CF/20Ar/60CHF/20N. The resist may then be removed with an anisotropic high density oxygen plasma.

Direct Imprinting Of Etch Barriers Using Step And Flash Imprint Lithography

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US Patent:
7163888, Jan 16, 2007
Filed:
Nov 22, 2004
Appl. No.:
10/995800
Inventors:
Kathy A. Gehoski - Gilbert AZ, US
William J. Dauksher - Mesa AZ, US
Ngoc V. Le - Gilbert AZ, US
Douglas J. Resnick - Gilbert AZ, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21/4763
US Classification:
438627, 438641, 438654
Abstract:
A direct imprinting process for Step and Flash Imprint Lithography includes providing () a substrate (); forming () an etch barrier layer () on the substrate; patterning () the etch barrier layer with a template () while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer () on the substrate; and performing () an etch to substantially remove the residual layer. Optionally, a patterning layer () may be formed on the substrate () prior to forming the etch barrier layer (). Additionally, an adhesive layer () may be applied () between the substrate () and the etch barrier layer ().

Disk Drive Identifying Starting Track By Performing Multiple Load Operations

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US Patent:
7209310, Apr 24, 2007
Filed:
Jul 25, 2005
Appl. No.:
11/188947
Inventors:
Chun Sei Tsai - Tustin CA, US
Ngoc Le - Fountain Valley CA, US
Jenghung Chen - Cupertino CA, US
Hien Chu - Santa Ana CA, US
Assignee:
Western Digital Technologies, Inc. - Lake Forest CA
International Classification:
G11B 21/02
US Classification:
360 75, 360 7808
Abstract:
A disk drive is disclosed comprising a disk having a plurality of servo sectors defining a plurality of servo tracks, wherein each servo sector comprises a track address identifying a corresponding servo track. A head is actuated over the disk, and a ramp is positioned near an outer diameter of the disk, wherein an edge of the ramp extends over a plurality of the servo tracks. The head is loaded from the ramp onto the disk, and a track address in at least one of the servo sectors is detected and stored. The process is repeated a number of times, and then a starting track proximate an outer diameter of the disk is identified in response to the detected and stored track addresses.

Integrated Multi-Wavelength Fabry-Perot Filter And Method Of Fabrication

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US Patent:
7378346, May 27, 2008
Filed:
Mar 22, 2006
Appl. No.:
11/387468
Inventors:
Ngoc V. Le - Gilbert AZ, US
Jeffrey H. Baker - Chandler AZ, US
Diana J. Convey - Laveen AZ, US
Paige M. Holm - Phoenix AZ, US
Steven M. Smith - Gilbert AZ, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438689, 216 2, 216 67, 356480
Abstract:
A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (). The method comprises forming a first mirror () over the substrate (). A plurality of etalon material layers () are formed over the mirror (), and a plurality of etch stop layers () are formed, one each between adjacent etalon material layers (). A photoresist is patterned to create an opening () over the top etalon material layer () and an etch () is performed down to the top etch stop layer (). An oxygen plasma () may be applied to convert the etch stop layer () within the opening () to silicon dioxide (). The photoresist patterning, etching, and applying of an oxygen plasma may be repeated as desired to obtain the desired number of levels (). A second mirror () is then formed on each of the levels ().

Voltage Stabilizer Memory Module

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US Patent:
7663939, Feb 16, 2010
Filed:
May 30, 2006
Appl. No.:
11/442818
Inventors:
Henry Nguyen - Fountain Valley CA, US
Ngoc Le - Irvine CA, US
Assignee:
Kingston Technology Corporation - Fountain Valley CA
International Classification:
G11C 7/00
US Classification:
36518911, 365222
Abstract:
A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory components, the VSC for ensuring that the plurality of memory components operate at their optimum performance level. A voltage stabilizer memory module (VSMM) in accordance with the present invention includes a printed circuit board (PCB) that contains memory chips, discrete components, a voltage stabilizer converter, and other related components. The voltage stabilizer converter uses system voltage supply as its input and its output is the voltage supply for the DRAM components. Accordingly, the VSSM is more adaptable, more stable and has better performance than conventional memory modules.

Memory-Module Extender Card For Visually Decoding Addresses From Diagnostic Programs And Ignoring Operating System Accesses

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US Patent:
8396998, Mar 12, 2013
Filed:
Dec 10, 2010
Appl. No.:
12/965699
Inventors:
Jerry N. Le - Irvine CA, US
Ngoc V. Le - Irvine CA, US
Tat Leung Lai - Torrance CA, US
Ramon S. Co - Trabuco Canyon CA, US
Assignee:
Kingston Technology Corp. - Fountain Valley CA
International Classification:
G06F 3/00
G06F 5/00
US Classification:
710 15, 710 2, 710 17
Abstract:
A diagnostic extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module and an intercepting decoder chip that receives the chip-select (CS) from the motherboard that selects the memory module for access. When CS is activated, the intercepting decoder chip illuminates a visual indicator on the extender card, allowing a user to locate a memory module being accessed. The exact translation or mapping from logical addresses of test programs to physical addresses of the memory modules is not needed, since the visual indicator shows which memory module is really being accessed, regardless of proprietary address mapping by north bridge chips. Operating system memory accesses are filtered out by a counter that counts accesses during a period set by a timer. When the number of accesses exceeds a threshold, the visual indicator is lit.

Selective Etch Process For Step And Flash Imprint Lithography

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US Patent:
20050277066, Dec 15, 2005
Filed:
Jun 10, 2004
Appl. No.:
10/866563
Inventors:
Ngoc Le - Gilbert AZ, US
William Dauksher - Mesa AZ, US
Doug Resnick - Gilbert AZ, US
International Classification:
G03F007/00
G03F007/36
US Classification:
430316000, 430313000
Abstract:
A selective etch process for step and flash imprint lithography includes providing () a substrate (); forming () a transfer layer () on the substrate; forming () an etch barrier layer () on the transfer layer; patterning () the etch barrier layer with a template () while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer () on the transfer layer; performing () an etch to substantially remove the residual layer; and performing () an etch with a mixture of nitrogen and hydrogen, and more preferably NH, to substantially remove the portion of the transfer layer not underlying the etch barrier layer.
Ngoc Thi Minh Le from Walnut, CA, age ~38 Get Report