Naichih C Chang

7643410, Jan 5, 2010

Mar 29, 2006

11/394057

Naichih Chang - Shrewsbury MA, US
Pak-Lung Seto - Shrewsbury MA, US

Intel Corporation - Santa Clara CA

H04J 1/16

370229, 370248, 370467, 710309, 710310

A bridge for translating a first storage protocol to a second protocol includes an affiliation manager. The affiliation manager accepts a connection from a host and establishes a connection between a device that uses the second protocol and the host that uses the second protocol. The affiliation manager monitors commands received from the host and responses received from the device on the connection. Upon detecting no pending commands for the device, the bridge may close the connection to the host if there is another host requesting a new connection to the device and establish the new connection between the device and the other host.

7650540, Jan 19, 2010

Jul 21, 2006

11/490892

Luke L. Chang - Marlboro MA, US
Pak-Lung Seto - Shrewsbury MA, US
Naichih Chang - Shrewsbury MA, US

Intel Corporation - Santa Clara CA

G01R 31/28

714716, 714 5, 714 30, 714 43, 714 56, 714799, 714712, 714718, 714719, 714735, 365201, 375224, 370241, 370249

A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at least one loopback mode; defining, by the far end device, a reserved and/or error state if both of the bits are set; and processing, by the far end device, the two bits together to determine if the two bits are in a state that defines at least one loopback mode or if the two bits are set. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

7676604, Mar 9, 2010

Nov 22, 2005

11/285825

William Halleck - Lancaster MA, US
Victor Lau - Marlboro MA, US
Pak-Lung Seto - Shrewsbury MA, US
Naichih (Neil) Chang - Shrewsbury MA, US

Intel Corporation - Santa Clara CA

G06F 3/00
G06F 15/16

710 5, 709200

A method and apparatus for managing task context are provided. Upon initialization, a protocol engine provides context resources available for processing tasks to a task issuer. Based on available context resources, the task issuer creates and manages a free list of available task context indices and assigns an index to a task prior to storing task context in a context memory accessible to both the task issuer and the protocol engine and issuing the task to the protocol engine.

7730239, Jun 1, 2010

Jun 23, 2006

11/474013

Naichih Chang - Shrewsbury MA, US
Pak-Lung Seto - Shrewsbury MA, US
Victor Lau - Marlboro MA, US

Intel Corporation - Santa Clara CA

G06F 3/00

710 53

An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.

7738502, Jun 15, 2010

Sep 1, 2006

11/514579

Naichih Chang - Shrewsbury MA, US
Pak-Lung Seto - Shrewsbury MA, US
Luke L. Chang - Marlboro MA, US

Intel Corporation - Santa Clara CA

H04L 7/00

370503, 370216, 370252, 375371, 375350

A noise filtering system provides adaptive noise filtering in the physical layer of serial and parallel interfaces for storage protocol applications. The system provides adaptive noise filtering for both hot plug and hot removal applications.

7747788, Jun 29, 2010

Jun 30, 2005

11/172627

Naichih Chang - Shrewsbury MA, US
Victor Lau - Marloboro MA, US
Pak-lung Seto - Shrewsbury MA, US

Intel Corporation - Santa Clara CA

G06F 3/00
G06F 13/28

710 5, 711120

Methods and apparatus for target-side SATA NCQ tag management are disclosed. In one aspect, an apparatus may include a status memory and a status manager circuit in communication with the status memory. The status memory may store status information for each of a plurality of commands that have been queued according to Native Command Queuing (NCQ). The status information may indicate whether or not each of the commands has been completed. The status manager circuit may generate and provide a status signal based on the status information stored in the status memory. Systems including such an apparatus and other components, such as hard disks, are also disclosed.

7797463, Sep 14, 2010

Jun 30, 2005

11/170851

William Halleck - Lancaster MA, US
Pak-lung Seto - Shrewsbury MA, US
Victor Lau - Marlboro MA, US
Naichih Chang - Shrewsbury MA, US

Intel Corporation - Santa Clara CA

G06F 3/00
G06F 13/12
H04J 3/16

710 30, 710 74, 710 36, 710 37, 710 38, 710 52, 370466, 370467, 370469

A device includes a task context controller, at least one transport engine connected to the task context controller, and at least one comparator connected to the transport engine. The comparator to compare a data offset from a receive frame with a current data offset and a result is used to determine frame processing order.

7805543, Sep 28, 2010

Jun 30, 2005

11/172715

Naichih Chang - Shrewsbury MA, US
Victor Lau - Marlboro MA, US
Pak-lung Seto - Shrewsbury MA, US

Intel Corporation - Santa Clara CA

G06F 3/00
G06F 13/00
G06F 5/00
G06F 13/12
G06F 13/38

710 6, 710 34, 710 49, 710 74

Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.