Ling Wang

6993108, Jan 31, 2006

Dec 3, 2001

10/006516

Kuang Chi - San Jose CA, US
Ling Wang - Sunnyvale CA, US
Antony Davies - Campbell CA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03D 3/24

375376, 375374, 375375

In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An upcounter generates an UPCNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A downcounter generates a DOWNCNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal. One of a FWD (forward) signal or a BWD (backward) signal are asserted or are both not asserted depending on the UPCNT value and the DNCNT value in comparison to the TBW value and the DBW value. Another clock signal having a leading phase from the current ACLK signal is selected as a new ACLK (recovered clock) signal when the FWD signal is asserted.

7003066, Feb 21, 2006

Dec 3, 2001

10/006559

Antony Davies - Campbell CA, US
Chienkuang Chen - Sunnyvale CA, US
Ling Wang - Sunnyvale CA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03D 3/24

375376, 375374, 375375

In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.

7792856, Sep 7, 2010

Jun 29, 2007

11/771668

Ariel Fuxman - San Jose CA, US
Peter Jay Haas - San Jose CA, US
Berthold Reinwald - San Jose CA, US
Yannis Sismanis - San Jose CA, US
Ling Wang - San Jose CA, US

International Business Machines Corporation - Armonk NY

G06F 17/30
G06F 7/00

707769, 707602, 707718

A method is disclosed for conducting a query to transform data in a pre-existing database, the method comprising: collecting database information from the pre-existing database, the database information including inconsistent dimensional tables and fact tables; running an entity discovery process on the inconsistent dimensional tables and the fact tables to produce entity mapping tables; using the entity mapping tables to resolve the inconsistent dimensional tables into resolved dimensional tables; and running the query on a resolved database to obtain a query result, the resolved database including the resolved dimensional table.

7910267, Mar 22, 2011

Dec 12, 2008

12/333699

Xianzhong Zeng - Fremont CA, US
Hai Sun - Milpitas CA, US
Hongping Yuan - Fremont CA, US
Dujiang Wan - Fremont CA, US
Ling Wang - Hercules CA, US

Western Digital (Fremont), LLC - Fremont CA

G03F 1/00

430 5, 430320

An optical mask for providing a pattern for portion of an electronic device, such as a magnetic recording transducer, is disclosed. The optical mask includes a device feature and at least one detached correction feature. The device feature includes a corner corresponding to a device corner of the pattern. The device corner has an angle of greater than zero degrees and less than one hundred eighty degrees. The at least one detached correction feature resides in proximity to but is physically separated from the corner. Each of the at least one detached correction feature is sub-resolution.

7979436, Jul 12, 2011

Jun 5, 2008

12/133552

Ariel Fuxman - San Jose CA, US
Peter Jay Haas - San Jose CA, US
Berthold Reinwald - San Jose CA, US
Yannis Sismanis - San Jose CA, US
Ling Wang - San Jose CA, US

International Business Machines Corporation - Armonk NY

G06F 7/00

707737

A method is disclosed for conducting a query to transform data in a pre-existing database, the method comprising: collecting database information from the pre-existing database, the database information including inconsistent dimensional tables and fact tables; running an entity discovery process on the inconsistent dimensional tables and the fact tables to produce entity mapping tables; using the entity mapping tables to resolve the inconsistent dimensional tables into resolved dimensional tables; and running the query on a resolved database to obtain a query result, the resolved database including the resolved dimensional table.

8274412, Sep 25, 2012

Jan 10, 2011

12/987393

Fulong Zhang - Upper Macungie PA, US
Ling Wang - Sunnyvale CA, US
John Schadt - Bethlehem PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03M 9/00

341101, 341100

In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N−1 operating mode (that serializes (N−1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.

8322023, Dec 4, 2012

Nov 10, 2009

12/615544

Xianzhong Zeng - Fremont CA, US
Yunhe Huang - Pleasanton CA, US
Ling Wang - Hercules CA, US
Hai Sun - Milpitas CA, US

Western Digital (Fremont), LLC - Fremont CA

G11B 5/127
H04R 31/00

2960316, 28960312, 28960314, 28960315, 28960318, 216 62, 216 65, 216 66, 360121, 360122, 360317, 451 5, 451 41

A method for fabricating a magnetic transducer is described. The magnetic transducer includes a pole having a pole tip and a flared region. The method Includes providing a first mask layer on the pole and providing a second mask layer on the first mask layer. The first mask layer is soluble in a predetermined solution and has a first thickness. The second mask layer has a second thickness greater than the first thickness. The method also includes forming a mask from the first mask layer and the second mask layer. The step of forming the mask layer includes using the predetermined solution. The mask has a pattern that exposes a portion of the pole tip and covers a portion of the flared region. The method also includes providing a wrap-around shield on at least the pole tip.

8394280, Mar 12, 2013

Nov 6, 2009

12/614210

Dujiang Wan - Fremont CA, US
Hai Sun - Milpitas CA, US
Hongping Yuan - Fremont CA, US
Ling Wang - Hercules CA, US
Xianzhong Zeng - Fremont CA, US

Western Digital (Fremont), LLC - Fremont CA

B44C 1/22

216 22, 216 41, 216 47, 216 57, 216 67, 216 72, 216 83, 216 95, 438694, 438703, 438736, 438737, 438738

Methods of patterning a material are disclosed. A first resist pattern is formed on a field. A protective layer is formed over the first resist pattern and at least a portion of the field. A second resist pattern is formed over a portion of the protective layer. A portion of a material to be patterned deposited adjacent to the first and second resist patterns is removed.