Ming Cheu Chen

6915335, Jul 5, 2005

Sep 17, 2001

09/955004

Ming Chi Chen - Union City CA, US
Robert Chen - Fremont CA, US
Sanjoy Dey - Fremont CA, US
James Everett Grishaw - Santa Clara CA, US
Mick Henniger - Buchanan Dam TX, US

Cisco Technology, Inc. - San Jose CA

G06F015/16

709213, 709250, 709229, 710 8, 710 10, 710 11, 710 15

A method and apparatus for implementing host management of an intelligent daughtercard utilizes a high-speed serial link and a defined plurality of serial protocol commands to provide high bandwidth control path for management of daughtercard memory and application specific initialization and/or configuration changes.

7108559, Sep 19, 2006

Dec 21, 2004

11/020733

Helen Shtargot - Foster City CA, US
Dattatri Mattur - Sunnyvale CA, US
Shawn Bender - Campbell CA, US
William J. Lewis - Mountain View CA, US
Lwin Tint - Newark CA, US
David Tarkington - Sunnyvale CA, US
Ming Chi Chen - Union City CA, US
Rene Duzac - San Jose CA, US
James Everett Grishaw - Santa Clara CA, US
Torence Lu - Fremont CA, US
Kimberly Rae Turner - Apex NC, US
Phong Hoang Ho - Cary NC, US
Robert A. Loose - Cary NC, US
Stephen Scearce - Apex NC, US

Cisco Technology, INc. - San Jose CA

H01R 25/00
H01R 12/00
H01R 27/02
H01R 31/00
H05K 1/00

439638, 439 69

A router includes WIC and Network Module slots that be reconfigured to hold cards and network modules having different form factors. A motherboard/midplane arrangement provides for a field replaceable motherboard that can be replaced without removing the router from the rack.

7285022, Oct 23, 2007

Sep 18, 2006

11/523320

Helen Shtargot - Foster City CA, US
Shawn Bender - Campbell CA, US
William J. Lewis - Mountain View CA, US
Lwin Tint - Newark CA, US
David Tarkington - Sunnyvale CA, US
Ming Chi Chen - Union City CA, US
Rene Duzac - San Jose CA, US
James Everett Grishaw - Santa Clara CA, US
Torence Lu - Fremont CA, US
Kimberly Rae Turner - Dublin OH, US
Phong Hoang Ho - Cary NC, US
Robert A. Loose - Cary NC, US
Stephen Scearce - Apex NC, US
Terri Cruse - Lathrop CA, US

Cisco Technology, Inc. - San Jose CA

H01R 25/00

439638

A network device includes card slots and Network Module slots that be reconfigured to hold cards and network modules having different form factors.

7333106, Feb 19, 2008

Mar 27, 2003

10/402304

Tsailai Terry Wu - San Jose CA, US
Ming Chen - San Jose CA, US

Silicon Motion, Inc. - Milpitas CA

G06T 15/40

345422, 345421, 345531, 345532, 345536, 345542, 345559

In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The apparatus also includes control logic coupled to the Z-buffer memory, the set of bits, and the init register. The control logic sets the set of bits upon receipt of an initialization request. The control logic retrieves a Z value from either the init register or from the Z-buffer memory according to the states of the set of bits.

7515940, Apr 7, 2009

Mar 22, 2005

11/086489

Ming Chi Chen - Union City CA, US
Mickey Ramal Henniger - Buchanan Dam TX, US

Cisco Technology, Inc. - San Jose CA

H04M 1/00

4555621, 455101, 375299

A system and method for selecting a best transmit antenna for a transceiver using antenna diversity that caches the identity of the best transmit antenna for each remote node from which a message has been received. The best transmit antenna is then selected for each message sent to a remote node having a cache entry.

7577726, Aug 18, 2009

Feb 7, 2002

10/071811

Theodore Conard - Milpitas CA, US
Ming Chi Chen - Union City CA, US

Cisco Technology, Inc. - San Jose CA

G06F 15/177

709221, 709238

In a method for updating a hardware configuration of a networked communications device, a networked communications device is provided with one or more programmable logic units. A first hardware configuration is determined which describes hardware features programmed into the programmable logic unit. When an updated hardware configuration becomes available, it can be downloaded into a centralized file holding configuration information for the main circuit board and add-in options cards of the networked device. The programmable logic unit is re-programmed with the second hardware configuration to provide an updated hardware configuration.

7680051, Mar 16, 2010

Feb 28, 2007

11/711959

Nipa Kumar - Santa Clara CA, US
Randall Stewart - Chapin SC, US
Peter Lei - Arlington Heights IL, US
Ming Chen - Fremont CA, US
Kenneth Durazzo - San Ramon CA, US

Cisco Technology, Inc. - San Jose CA

H04L 12/28
H04J 3/24

370236, 370392, 370474

In one embodiment, a method can include: (i) pre-configuring a stream control transmission protocol (SCTP) association; (ii) receiving a transmission control protocol (TCP) packet in a network device, where the TCP packet is intended for a destination node; (iii) encapsulating the TCP packet into an SCTP payload; and (iv) transmitting the SCTP payload across a wide area network (WAN).

7746355, Jun 29, 2010

Jan 24, 2007

11/657966

Mike Cai - Newark CA, US
Lin Tan - Cupertino CA, US
Frido Garritsen - Hayward CA, US
Ming Chen - San Jose CA, US

Vivante Corporation - Sunnyvale CA

G09G 5/00

345620, 345623, 345624

A distributed clipping scheme is provided, view frustum culling is distributed in several places in a graphics processing pipeline to simplify hardware implementation and improve performance. In general, many 3D objects are outside viewing frustum. In one embodiment, clipping is performed on these objects with a simple algorithm in the PA module, such as near Z clipping, trivial rejection and trivial acceptance. In one embodiment, the SE and RA modules perform the rest of clipping, such as X, Y and far Z clipping. In one embodiment, the SE module performs clipping by way of computing a initial point of rasterization. In one embodiment, the RA module performs clipping by way of conducting the rendering step of the rasterization process. This approach distributes the complexity in the graphics processing pipeline and makes the design simpler and faster, therefore design complexity, cost and performance may all be improved in hardware implementation.