Min Ling Yang

6707075, Mar 16, 2004

Dec 10, 2002

10/317665

Dennis L. Rogers - New York NY
Min Yang - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

H01L 2166

257117, 257438, 438 16, 438 42, 438 45

A method of forming an avalanche trench optical detector device on a semiconductor substrate, comprising forming a first set and a second set of trenches in the substrate, wherein trenches of the first set are alternately disposed with respect to trenches of the second set, filling the trenches with a doped sacrificial material, and annealing the device to form a multiplication region in the substrate. The method comprises etching the doped sacrificial material from the first set of trenches, filling the first set of trenches with a doped material of a first conductivity, etching the doped sacrificial material from a second set of trenches, and filling the second set of trenches with a doped material of a second conductivity. The method further comprises providing separate wiring connections to the first set of trenches and the second set of trenches.

6946696, Sep 20, 2005

Dec 23, 2002

10/328285

Kevin K. Chan - Staten Island NY, US
Guy M. Cohen - Mohegan Lake NY, US
Meikei Ieong - Wappingers Falls NY, US
Ronnen A. Roy - Ossining NY, US
Paul Solomon - Yorktown Heights NY, US
Min Yang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01C027/148

257250, 257365, 257288, 257412, 257388, 257347, 438157, 438283, 438279, 438299

A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

7087965, Aug 8, 2006

Apr 22, 2004

10/830347

Kevin K. Chan - Staten Island NY, US
Meikei Ieong - Wappingers Falls NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Leathen Shi - Yorktown Heights NY, US
Min Yang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 27/01
H01L 27/12
H01L 31/0392

257347, 257348, 257349, 257350, 257351, 257352, 257353, 257354, 257627, 257628

Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

7187059, Mar 6, 2007

Jun 24, 2004

10/875727

Kevin K. Chan - Staten Island NY, US
Kathryn W. Guarini - Yorktown Heights NY, US
Meikel Ieong - Wappinger Falls NY, US
Kern Rim - Yorktown Heights NY, US
Min Yang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 29/04
H01L 31/036
H01L 29/06
H01L 31/0328
H01L 31/0336

257628, 257 18, 257 19, 257627, 257750, 257798

A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600 C. and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described including the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HCL acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a root mean square (RMS) surface roughness of less than 0. 1 run.

7259049, Aug 21, 2007

Jun 7, 2005

11/146624

Kevin K. Chan - Staten Island NY, US
Guy M. Cohen - Mohegan Lake NY, US
Meikei Ieong - Wappingers Falls NY, US
Ronnen A. Roy - Ossining NY, US
Paul M Solomon - Yorktown Heights NY, US
Min Yang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 21/84

438157, 257E21415, 438164, 438233

A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

7402466, Jul 22, 2008

Jul 25, 2006

11/492271

Kevin K. Chan - Staten Island NY, US
Meikei Ieong - Wappingers Falls NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Leathen Shi - Yorktown Heights NY, US
Min Yang - Yorktown Heights NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438149, 438150, 438152, 438154, 438199, 438222, 438256, 438275, 438424, 438479, 438510

Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

7691688, Apr 6, 2010

Jun 23, 2008

12/143912

Kevin K. Chan - Staten Island NY, US
Meikei Ieong - Wappingers Falls NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Leathen Shi - Yorktown Heights NY, US
Min Yang - Mahopac NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00

438150, 438166, 438187, 438198, 438199, 438486, 257347, 257348, 257349, 257350, 257351, 257352, 257353, 257354, 257482, 257627, 257628, 257E29003, 257E29004, 257E29298, 257E21036, 257E21233

Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

7791057, Sep 7, 2010

Apr 22, 2008

12/107573

Hsiang-Lan Lung - Elmsford NY, US
Chung Hon Lam - Peekskill NY, US
Min Yang - Yorktown Heights NY, US
Alejandro G. Schrott - New York NY, US

Macronix International Co., Ltd. - Hsinchu
International Business Machines Corporation - Armonk NY

H01L 29/02

257 2, 257 3, 257 4, 257E2917, 257E27004, 365148, 438574, 438579

Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.