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Min Xian Cao

from San Francisco, CA
Age ~44
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Also known as:
Min X Cao, Minxian Cao
Phone and address:
1230 Ortega St, San Francisco, CA 94122
(415) 681-6582
Related to:
Pei Cao, 54Dan Boneh, 54
Connected to:
Alain A Cao, 39Alex T Cao, 51Alexandra H Cao, 35Anne M Cao, 49Annie N Cao, 50Ben T Cao, 55Cam D Cao, 70Carol A Cao, 45Chen Cao, 51Chieu X Cao, 61

Min Cao Phones & Addresses

  • 1230 Ortega St, San Francisco, CA 94122 (415) 681-6582

Resumes

Resumes

Min Cao Photo 1

Min Cao

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Location:
San Francisco, CA
Industry:
Medical Devices
Work:
Abbott Oct 2015 - May 2015
Regulatory Affairs Specialist
Biotronik Medical Device Jul 2012 - Nov 2014
Regulatory Affairs Assistant
Education:
Shaanxi Normal University
Bachelors, Bachelor of Science Beihang University
Masters, Biomedical Engineering
Skills:
法规事务
医疗设备
生物技术
Min Cao Photo 2

Staff Software Engineer

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Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Linkedin Feb 2015 - Mar 2016
Senior Software Engineer
Google Feb 2015 - Mar 2016
Staff Software Engineer
Vmware Nov 2013 - Feb 2015
Staff Engineer
Aruba, A Hewlett Packard Enterprise Company Apr 2012 - Nov 2013
Senior Software Engineer
Cisco Sep 2007 - Apr 2012
Senior Software Engineer
Education:
University of Illinois at Urbana - Champaign 2001 - 2007
Doctorates, Doctor of Philosophy, Computer Engineering Tsinghua University 1998 - 2001
Master of Science, Masters, Electrical Engineering Tsinghua University 1994 - 1998
Skills:
Distributed Systems
Java
Python
C/C++ Stl
Object Oriented Design
Cloud Computing
Virtualization
Embedded Systems
Linux Kernel
L2/L3 Protocols
Statistical Modeling
Stream Processing
Apache Kafka
Apache Samza
Hadoop
Big Data
Nosql
Lucene
Recommender Systems
Scalable Architecture
Restful Architecture
Vmware Vsphere
Location Based Services
Software Defined Network
Wifi
Data Mining
Log Analysis
Optimizing Performance
Git
Intellij Idea
Languages:
English
Mandarin
Min Cao Photo 3

Engineer

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Location:
4041 east White St, Champaign, IL 61821
Industry:
Computer Networking
Work:
Cisco
Engineer
Education:
University of Illinois at Urbana - Champaign 2001 - 2007
Skills:
Oracle Dba
Dba
Software
Min Cao Photo 4

Engineer

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Location:
San Francisco, CA
Industry:
Internet
Work:
Healthvision
Engineer
Huatek Software Engineering Co., Ltd. 2002 - 2009
Senior Software Engineer
Min Cao Photo 5

Senior Member Of Consulting Staff At Cadence Design Systems

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Location:
San Francisco Bay Area
Industry:
Semiconductors
Min Cao Photo 6

Min Cao

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Publications

Us Patents

Photo Diode Pixel Sensor Array Having A Guard Ring

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US Patent:
6545711, Apr 8, 2003
Filed:
Nov 2, 1998
Appl. No.:
09/184426
Inventors:
Frederick A. Perner - Palo Alto CA
Min Cao - Mountain View CA
Charles M. C. Tan - Santa Clara CA
Jeremy A. Theil - Mountain View CA
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H04N 5335
US Classification:
348294, 257459, 257233
Abstract:
An image sensor array. The image sensor array includes a substrate. An array of photo diode sensors are electrically interconnected to the substrate. The photo diode sensors conduct charge at a rate proportional to the intensity of light received by the photo diode sensors. A ring of guard diodes are located around the periphery of the array of photo diode sensors. Each guard diode has a guard diode anode connected to a predetermined guard anode voltage and a guard diode cathode connected to a static guard cathode voltage.

Amorphous Semiconductor Open Base Phototransistor Array

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US Patent:
7038242, May 2, 2006
Filed:
Feb 28, 2001
Appl. No.:
09/795608
Inventors:
Paul J. Vande Voorde - San Mateo CA, US
Frederick A. Perner - Palo Alto CA, US
Dietrich W. Vook - Menlo Park CA, US
Min Cao - Mountain View CA, US
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H01L 27/15
H01L 31/12
H01L 33/00
US Classification:
257 79, 257 88
Abstract:
An array of light-sensitive sensors utilizes bipolar phototransistors that are formed of multiple amorphous semiconductor layers, such as silicon. In the preferred embodiment, the bipolar transistors are open base devices. In this preferred embodiment, the holes that are generated by reception of incoming photons to a particular open base phototransistor provide current injection to the base region of the phototransistor. The collector region is preferably an intrinsic amorphous silicon layer. The phototransistors may be operated in either an integrating mode in which bipolar current is integrated or a static mode in which a light-responsive voltage is monitored.

Method And System For Parallel Processing Of Ic Design Layouts

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US Patent:
7657856, Feb 2, 2010
Filed:
Sep 12, 2006
Appl. No.:
11/520487
Inventors:
Mathew Koshy - San Mateo CA, US
Roland Ruehl - San Carlos CA, US
Min Cao - San Ramon CA, US
Li-Ling Ma - San Jose CA, US
Eitan Cadouri - Cupertino CA, US
Tianhao Zhang - Raleigh NC, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 7, 716 8, 716 21, 703 16
Abstract:
Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Dual-Pattern Coloring Technique For Mask Design

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US Patent:
8429574, Apr 23, 2013
Filed:
Apr 14, 2011
Appl. No.:
13/087324
Inventors:
Min Cao - San Ramon CA, US
Jeffrey Markham - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose
International Classification:
G06F 17/50
US Classification:
716 54, 716 52, 716112, 716119, 430 5
Abstract:
A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Methods, Systems, And Articles Of Manufacture For Implementing Constraint Checking Windows For An Electronic Design For Multiple-Patterning Lithography Processes

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US Patent:
8516404, Aug 20, 2013
Filed:
Dec 30, 2011
Appl. No.:
13/341849
Inventors:
Min Cao - San Ramon CA, US
Roland Ruehl - San Carlos CA, US
Gilles S. C. Lamant - Sunnyvale CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 52, 716 50, 716 51, 716 54, 716 55
Abstract:
Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.

Methods, Systems, And Computer Program Products For Implementing Interactive Coloring Of Physical Design Components In A Physical Electronic Design With Multiple-Patterning Techniques Awareness

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US Patent:
8645902, Feb 4, 2014
Filed:
Apr 12, 2012
Appl. No.:
13/445847
Inventors:
Henry Yu - Palo Alto CA, US
Jeffrey Markham - San Jose CA, US
Min Cao - San Ramon CA, US
Roland Ruehl - San Carlos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 15/04
US Classification:
716139, 716 55
Abstract:
Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.

Method, System, And Program Product For Interactive Checking For Double Pattern Lithography Violations

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US Patent:
20110219341, Sep 8, 2011
Filed:
Mar 8, 2010
Appl. No.:
12/719710
Inventors:
Min CAO - San Ramon CA, US
Roland RUEHL - San Carlos CA, US
Assignee:
CADENCE DESIGN SYSTEMS, INC. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 50
Abstract:
Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Transistorless Memory Cell

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US Patent:
20210366529, Nov 25, 2021
Filed:
Aug 3, 2021
Appl. No.:
17/392583
Inventors:
- Hsin-Chu, TW
Chung Te Lin - Tainan City, TW
Min Cao - Martinez CA, US
Yuh-Jier Mii - Hsin-Chu, TW
Sheng-Chih Lai - Hsinchu County, TW
International Classification:
G11C 11/16
H01L 27/22
H01L 43/12
H01L 43/02
Abstract:
In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.
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Min Xian Cao from San Francisco, CA, age ~44 Get Report