Yang Lu

7868378, Jan 11, 2011

Jul 17, 2006

11/488378

Marco A. Zuniga - Fremont CA, US
Budong You - Fremont CA, US
Yang Lu - Fremont CA, US

Volterra Semiconductor Corporation - Fremont CA

H01L 29/66
H01L 21/02
H01L 21/84
H01L 21/8238

257328, 257492, 257493, 257339, 257557, 257611, 257E29187, 257E29261, 257E21373, 257E21452, 438163, 438204, 438236, 438327, 438335

An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

8431450, Apr 30, 2013

Jan 10, 2011

12/987905

Marco A. Zuniga - Fremont CA, US
Budong You - Fremont CA, US
Yang Lu - Fremont CA, US

Volterra Semiconductor Corporation - Fremont CA

H01L 29/66
H01L 21/02
H01L 21/84
H01L 21/8238

438163, 257328, 257333, 257493, 257557, 257611, 257E29187, 257E29261, 257E21373, 257E21452, 438204, 438236, 438316, 438325, 438327, 438335

An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

8647950, Feb 11, 2014

Aug 10, 2012

13/572428

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US

Volterra Semiconductor Corporation - Fremont CA

H01L 21/336

438270, 438286, 438589, 257E21621

A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

20070094664, Apr 26, 2007

Oct 21, 2005

11/256631

Kimming So - Palo Alto CA, US
Baobinh Truong - San Jose CA, US
Yang Lu - Palo Alto CA, US
Hon-Chong Ho - Fremont CA, US
Li-Hung Chang - Santa Clara CA, US
Chia-Cheng Choung - Fremont CA, US
Jason Leonard - San Jose CA, US

G06F 9/46

718103000

A first thread processor of a multi-thread processor system is operable to execute a first process, and a second thread processor of the multi-thread processor system is operable to execute a second process. A control register is operable to store priority information that is individually associated with at least one of the first thread processor and the second thread processor. The priority information identifies a prioritization of the first thread processor and/or a restriction on the second thread processor in a use of a shared hardware resource during execution of at least one of the first process and the second process.

20090224333, Sep 10, 2009

Jan 14, 2009

12/353866

Yang Lu - Fremont CA, US
Budong You - Fremont CA, US
Marco A. Zuniga - Palo Alto CA, US
Hamza Yilmaz - Saratoga CA, US

H01L 27/105
H01L 21/265
H01L 29/78

257392, 438514, 257E29255, 257E27081, 257E21334, 257368

A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.

20130105887, May 2, 2013

Aug 10, 2012

13/572015

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US

Volterra Semiconductor Corporation - Fremont CA

H01L 29/78
H01L 29/66

257330, 438270

Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

20130105888, May 2, 2013

Aug 10, 2012

13/572110

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US

Volterra Semiconductor Corporation - Fremont CA

H01L 29/78

257330, 257335

The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

20130109143, May 2, 2013

Aug 10, 2012

13/572281

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US
John Xia - Fremont CA, US

Volterra Semiconductor Corporation - Fremont CA

H01L 29/78

438270

The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.