Loi Le Phones & Addresses
-
San Jose, CA
Publications
Us Patents
Power Down Circuit For High Output Impedence State Of I/O Driver
View pageUS Patent:
20030071660, Apr 17, 2003
Filed:
Oct 15, 2001
Appl. No.:
09/978255
Inventors:
Loi Le - San Jose CA, US
Pekka Ojala - Fremont CA, US
Bahram Fotouhi - Cupertino CA, US
Pekka Ojala - Fremont CA, US
Bahram Fotouhi - Cupertino CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03B001/00
US Classification:
327/108000
Abstract:
A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P+/n-well diode.