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Qun Zhao Phones & Addresses

  • San Leandro, CA
  • San Francisco, CA

Resumes

Resumes

Qun Zhao Photo 1

Co-Founder And Vice President Of Fw Engineering

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Innogrit Corporation
Co-Founder and Vice President of Fw Engineering

Marvell Semiconductor
Senior Director, Engineering

Marvell Semiconductor 2005 - 2008
Senior Engineering Manager

Promise Technology 2001 - 2005
Senior Sw Manager
Education:
Beijing Institute of Technology 1986 - 1990
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Ssd
Sata
Pcie
System on A Chip
Embedded Systems
Linux
Storage
Application Specific Integrated Circuits
Usb
Product Management
Qun Zhao Photo 2

Qun Zhao

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Location:
San Francisco, CA
Industry:
Medical Devices
Qun Zhao Photo 3

Qun Zhao

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Qun Zhao Photo 4

Biotechnology Professional

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Location:
San Francisco Bay Area
Industry:
Biotechnology
Qun Zhao Photo 5

Student At Heald College

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Location:
San Francisco Bay Area
Industry:
Mental Health Care
Education:
Heald College 2008 - 2009

Business Records

Name / Title
Company / Classification
Phones & Addresses
Qun Zhao
Director of Engineering
Marvell Semiconductor, Inc
Mfg Electrical Measuring Instruments
5450 Bayfront Plz, Santa Clara, CA 95054
Qun Zhao
President
SCHIDERON ELECTRIC, INC
922 Sunset Crk Ln, Pleasanton, CA 94566
10440 S De Anza Blvd, Cupertino, CA 95014

Publications

Us Patents

Turbo Boot Systems And Methods For Subsequent Booting From A Captured Data Stored In A Non-Volatile Semiconductor Memory

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US Patent:
8417928, Apr 9, 2013
Filed:
Sep 21, 2009
Appl. No.:
12/563239
Inventors:
Qun Zhao - Pleasanton CA, US
Xinhai Kang - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 9/00
G06F 9/24
US Classification:
713 2, 713 1
Abstract:
A computer system includes a hard disk drive and a non-volatile semiconductor memory. The hard disk drive stores a first set of data that includes boot up data. The non-volatile semiconductor memory is distinct from semiconductor memory of the hard disk drive and semiconductor memory of a host of the computer system. A turbo boot driver module stores the boot up data in the non-volatile semiconductor memory and transfers the boot up data from the non-volatile semiconductor memory to a file system of the host during a boot up mode of the host.

Hibernation Or Suspend Using A Non-Volatile-Memory Device

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US Patent:
8443211, May 14, 2013
Filed:
Dec 11, 2009
Appl. No.:
12/636558
Inventors:
Qun Zhao - Pleasanton CA, US
Hsing-Yi Chiang - Taipei, TW
Xinhai Kang - San Jose CA, US
Chee Hoe Chu - San Jose CA, US
Lihan Chang - San Jose CA, US
Jin-Nan Liaw - San Jose CA, US
Robyn Jie Li - Cupertino, CA
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G06F 1/26
G06F 1/32
US Classification:
713300, 713320, 713324, 712228, 365228
Abstract:
This disclosure describes techniques for using a non-volatile-memory device such as flash memory to store memory data during hibernation or suspend. By so doing, hard drives and/or data are safer, and less power may be used.

Protection Against Data Corruption For Multi-Level Memory Cell (Mlc) Flash Memory

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US Patent:
8549214, Oct 1, 2013
Filed:
Feb 9, 2011
Appl. No.:
13/023905
Inventors:
Qun Zhao - Pleasanton CA, US
Xinhai Kang - Milpitas CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G06F 12/00
US Classification:
711103, 711E12007
Abstract:
Apparatus having corresponding methods and non-transitory computer-readable media comprise a flash controller configured to control a multi-level memory cell (MLC) flash memory, wherein the MLC flash memory includes a plurality of memory blocks, wherein each memory block includes a plurality of memory cells defining a plurality of pages, wherein each memory cell spans a group of the pages in one of the memory blocks, and wherein the flash controller comprises circuitry configured to receive data to be written to the MLC flash memory, select only one page, from each group of the pages, in one or to more of the memory blocks, and write the data only to the selected pages.

Virtualization Of Storage Devices

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US Patent:
20110138112, Jun 9, 2011
Filed:
Nov 19, 2010
Appl. No.:
12/950733
Inventors:
Hsing-Yi Chiang - Taipei, TW
Xinhai Kang - Milipitas CA, US
Qun Zhao - Pleasanton CA, US
International Classification:
G06F 12/00
US Classification:
711103, 711E12008
Abstract:
Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps logical block addresses to the SSD and to the disk drive. The technique includes determining, based on a file to be written to the logical drive, a target logical address that corresponds to one of the SSD and the disk drive, and writing the file to the logical drive at the target logical address to effect storage on one of the SSD and the disk drive.

Method And Apparatus For Effectively Increasing A Command Queue Length For Accessing Storage

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US Patent:
20130091307, Apr 11, 2013
Filed:
Oct 4, 2012
Appl. No.:
13/645370
Inventors:
MARVELL WORLD TRADE LTD. - St. Michael, BB
Xinhai Kang - Milpitas CA, US
Kanting Tsai - San Jose CA, US
Qun Zhao - Pleasanton CA, US
Assignee:
MARVELL WORLD TRADE LTD. - St. Michael
International Classification:
G06F 3/00
US Classification:
710 4
Abstract:
The present disclosure includes systems and techniques relating to effectively increasing a command queue length for accessing storage, such as by increasing the Queuing Depth (Q-Depth) of Native Command Queuing (NCQ) Commands. In some implementations, a method can comprise receiving a first command to access a first memory location of a storage device; receiving a second command to access a second memory location of a storage device; constructing a consolidated command including a memory address and a data transfer count associated with each of the first command and the second command; constructing an information command having consolidation information about the consolidated command; and communicating the information command and the consolidated command to the storage device for processing by the storage device.

Robustness-Aware Nand Flash Management

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US Patent:
20220223216, Jul 14, 2022
Filed:
Jan 13, 2021
Appl. No.:
17/147539
Inventors:
- Shanghai, CN
Lin Chen - Cupertino CA, US
Jie CHEN - Milpitas CA, US
Qun Zhao - Pleasanton CA, US
International Classification:
G11C 16/34
G11C 16/16
G11C 16/26
G06F 12/02
Abstract:
Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.

Voltage Drop Management For Vlsi And Soc

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US Patent:
20220206553, Jun 30, 2022
Filed:
Dec 30, 2020
Appl. No.:
17/137865
Inventors:
- Shanghai, CN
Lin Chen - Cupertino CA, US
Zhengtian Feng - Shanghai, CN
Qun Zhao - Pleasanton CA, US
International Classification:
G06F 1/30
G06F 3/06
Abstract:
Apparatus and methods are provided for managing voltage drops on a semiconductor chip. One exemplary embodiment according to the present disclosure may provide a method for managing voltage drops in a semiconductor chip. The method may comprise monitoring power supply voltages for different voltage domains in the semiconductor chip by a voltage drop detection circuit, determining that a voltage drop event has occurred based on voltage information and duration information associated with the voltage drop event reported from the voltage drop detection circuit, generating diagnostic information that includes whether the voltage drop event is an external event or an internal event determined based on the voltage information and timing information reported from the voltage drop detection circuit, and taking an action based on the diagnosis information.

Cache Program With Backup Blocks

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US Patent:
20220179762, Jun 9, 2022
Filed:
Dec 4, 2020
Appl. No.:
17/112123
Inventors:
- Shanghai, CN
Lin Chen - Cupertino CA, US
Jie Chen - Milpitas CA, US
Qun ZHAO - Pleasanton CA, US
International Classification:
G06F 11/20
G06F 3/06
Abstract:
Systems, apparatus and methods are provided for performing cache program operations in a non-volatile storage system. A method may comprise issuing a first cache program operation from a storage controller to a non-volatile storage device to write data to a first regular block, writing the data to the first regular block and a copy of the data to a backup block, determining that a program error has occurred while writing the data to the first regular block, asserting the program error to the storage controller, retrieving a mapping between the first regular block and the backup block, issuing a read operation to read the copy of the data from the backup block, reading the copy of the data from the backup block and issuing a second cache program operation to write the data to a second regular block and marking the first regular block as defective.
Qun Li Zhao from San Leandro, CA, age ~76 Get Report