Lei Tiffany Wu

7026839, Apr 11, 2006

Jun 26, 2003

10/606907

Lei Wu - Sunnyvale CA, US
Yonghua Song - Saratoga CA, US

Marvell International Ltd. - Hamilton

H03K 17/16

326 26, 326 82

Circuits, architectures, a system and methods for protecting against overvoltages in a high-speed differential signal or circuit. The circuit generally includes (a) a differential signal transmission line, (b) a common mode circuit coupled to and configured to reduce a swing of the differential signal transmission line, and (c) an overvoltage protection circuit coupled to the common mode circuit, wherein the common mode circuit is electrically interposed between the overvoltage protection circuit and the differential signal transmission line. The architectures and/or systems generally include an integrated circuit that embodies one or more of the inventive concepts disclosed herein. The method generally includes shunting the overvoltage to a ground potential through the termination circuit when the differential circuit receives the overvoltage, but otherwise processing the differential signal through circuitry coupled to the differential circuit. The present invention advantageously provides a satisfactory level of overvoltage protection for nearly all applications in which conventional CMOS circuitry can be used, while at the same time, having very little, if any, adverse effect on differential data signal transmission speed.

7167018, Jan 23, 2007

Feb 13, 2006

11/353736

Lei Wu - Sunnyvale CA, US
Yonghua Song - Saratoga CA, US

Marvell International Ltd. - Hamilton

H03K 17/16

326 26, 326 82

Circuits, architectures, a system and methods for protecting against overvoltages in a high-speed differential signal or circuit. The circuit generally includes (a) a differential signal transmission line, (b) a common mode circuit coupled to and configured to reduce a swing of the differential signal transmission line, and (c) an overvoltage protection circuit coupled to the common mode circuit, wherein the common mode circuit is electrically interposed between the overvoltage protection circuit and the differential signal transmission line. The architectures and/or systems generally include an integrated circuit that embodies one or more of the inventive concepts disclosed herein. The method generally includes shunting the overvoltage to a ground potential through the termination circuit when the differential circuit receives the overvoltage, but otherwise processing the differential signal through circuitry coupled to the differential circuit. The present invention advantageously provides a satisfactory level of overvoltage protection for nearly all applications in which conventional CMOS circuitry can be used, while at the same time, having very little, if any, adverse effect on differential data signal transmission speed.

7295644, Nov 13, 2007

Jul 14, 2003

10/619278

Lei Wu - Sunnyvale CA, US
Henri Sutioso - San Jose CA, US

Marvell International Ltd. - Hamilton

H03D 3/24

375375

Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes (a) a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, (b) a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and (c) an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of (1) sampling the data stream at predetermined times, (2) generating clock frequency information and clock phase information from sampled data, and (3) altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of the potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.

7319705, Jan 15, 2008

Oct 22, 2002

10/277449

Lei Wu - Sunnyvale CA, US
Timothy Hu - Los Altos CA, US

Marvell International Ltd. - Hamilton

H04J 3/04

370534, 710300

A high-speed serial ATA physical layer transmits data over a communications medium using a serial ATA protocol. A serial ATA control circuit controls operation of the serial ATA physical layer. A serial ATA multiplexer outputs a serial ATA signal and has a plurality of input lines for receiving input data and a control input that communicates with the serial ATA control circuit. A serial ATA analog front end includes a first differential driver that communicates with the serial ATA multiplexer and provides a first gain to the serial ATA signal and a serial ATA pre-emphasis circuit that provides pre-emphasis to the serial ATA signal to alter a transmission characteristic of the serial ATA signal.

7486718, Feb 3, 2009

Aug 4, 2003

10/634218

Pantas Sutardja - San Jose CA, US
Lei Wu - Sunnyvale CA, US
Hongying Sheng - San Jose CA, US

Marvell International Ltd. - Hamilton

H03K 11/00
H04L 25/60
H04L 25/64

375215, 375327, 375373, 375376, 4551803

Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal.

7733920, Jun 8, 2010

Sep 28, 2007

11/904886

Lei Wu - Sunnyvale CA, US
Timothy Hu - Los Altos CA, US

Marvell International Ltd. - Hamilton

H04J 3/04

370534, 710300

A high-speed serial ATA physical layer includes a serial ATA control circuit. A serial ATA multiplexer outputs one of a plurality of serial ATA signals that is selected by the serial ATA control circuit. A serial ATA analog front end provides a first gain and pre-emphasis to the selected one of the plurality of serial ATA signals. The pre-emphasis alters a transmission characteristic of the selected one of the plurality of serial ATA signals.

7835425, Nov 16, 2010

Dec 8, 2008

12/330218

Pantas Sutardja - San Jose CA, US
Lei Wu - Sunnyvale CA, US
Hongying Sheng - San Jose CA, US

Marvell International Ltd. - Hamilton

H03K 11/00
H04L 25/60
H04L 25/64

375215, 375376, 375373, 375327, 4551803

Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal.

7864912, Jan 4, 2011

Oct 19, 2007

11/975495

Lei Wu - Sunnyvale CA, US
Henri Sutioso - San Jose CA, US

Marvell International Ltd. - Hamilton

H03D 3/24

375375

Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of sampling the data stream at predetermined times, generating clock frequency information and clock phase information from sampled data, and altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of a potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.