Lei Wu

20120077824, Mar 29, 2012

Sep 22, 2011

13/200285

Dong Liang - Pearland TX, US
Lei Wu - Houston TX, US
Mathew Kizhakkekara Joseph - Houston TX, US
Jyothy Anie John - Houston TX, US

A61K 31/496
A61P 31/10

51425407

Provided herein is a pharmaceutical injectable formulation of itraconazole (10 mg/g) where the formulation comprises a solubilizer, a nonionic surfactant/emulsifier, a co-surfactant and a stabilizer. Further provided is a pharmaceutical formulation of itraconazole, said formulation comprising a solubilizer in a concentration of from about 20% to about 75%, a nonionic surfactant/emulsifier in a concentration of from about 20% to about 50%, a co-surfactant in a concentration from about 10% to about 45% and a stabilizer in a concentration of from about 1% to about 15%.

20120084110, Apr 5, 2012

Oct 3, 2011

13/252000

Lei Wu - Houston TX, US
Dong Dong - Sugar Land TX, US
David Jasper - Houston TX, US
Shaolong Dai - Houston TX, US

M3 TECHNOLOGY, INC. - Houston TX

G06Q 10/06

705 713

A system and method support smart scheduling for an oil, gas and chemical process system with a plurality of facility units. A subset of the process facility units can be selected from the plurality of process facility units. A partial scheduling calculation can be performed on the selected subset of process facility units, independently from the rest of the chemical process facility units. A schedule can be calculated for the subset of chemical process facility units, based on the partial scheduling calculation.

20210327525, Oct 21, 2021

Jun 30, 2021

17/364647

- Dallas TX, US
Lei Wu - Sugar Land TX, US

G11C 29/16
G11C 29/10
G01R 31/3185
G11C 29/32
G11C 29/12
G11C 29/26
G11C 29/02
G11C 29/14
G11C 29/36

A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

20190156908, May 23, 2019

Nov 15, 2018

16/192796

- Dallas TX, US
Lei Wu - Sugar Land TX, US

G11C 29/16
G11C 29/10
G11C 29/12
G11C 29/32
G01R 31/3185

A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.