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Lee Zhung Wang

from Diamond Bar, CA
Age ~64
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Also known as:
Lee Z Wang, Lee Marie Wang, Lee L Wang, Lee Shiang Chyong Luo, Lee W Luo, Zhung Wang Lee, Wang Luo Lee, Wang E
Phone and address:
1111 Ranchwood Pl, Pomona, CA 91765
(909) 396-6117
Related to:
Lee A Lay, 46
Connected to:
Adele R Wang, 107Aiyuan Wang, 52Akiet Wang, 74Alene P Wang, 52Amanda K Wang, 46Amei Wang, 61Amity H Wang, 70Amy Wang, 59Anastasia S Wang, 85Ange Wang, 35

Lee Wang Phones & Addresses

  • 1111 Ranchwood Pl, Diamond Bar, CA 91765 (909) 396-6117 (909) 612-1906
  • 957 Silvertip Dr, Diamond Bar, CA 91765 (909) 396-6117 (909) 860-0622
  • Pomona, CA
  • Austin, TX
  • Rosemead, CA
  • Irvine, CA
  • Eugene, OR
  • San Jose, CA
  • Hacienda Heights, CA
  • Hacienda Heights, CA
  • Los Angeles, CA

Professional Records

Medicine Doctors

Lee Wang Photo 1

Lee M. Wang

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Specialties:
Psychiatry
Work:
MSU HealthTeamOlin Student Health Services
463 E Cir Dr RM 123, East Lansing, MI 48824
(517) 884-6546 (phone), (517) 432-9460 (fax)
Education:
Medical School
Wayne State University School of Medicine
Graduated: 1999
Procedures:
Psychiatric Therapeutic Procedures
Conditions:
Anxiety Dissociative and Somatoform Disorders
Anxiety Phobic Disorders
Attention Deficit Disorder (ADD)
Bipolar Disorder
Depressive Disorders
Languages:
English
Description:
Dr. Wang graduated from the Wayne State University School of Medicine in 1999. He works in East Lansing, MI and specializes in Psychiatry.
Lee Wang Photo 2

Lee Ming-Li Wang

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Specialties:
Psychiatry
Education:
Wayne State University (1999)

Business Records

Name / Title
Company / Classification
Phones & Addresses
Lee Wang
Executive
Espritv8.com
Individual and Family Social Services
225 West 3Rd. Street Suite #302, Long Beach, CA 90802
Website: espritv8.com
Lee Wang
Executive
Espritv8.com
Individual and Family Social Services
225 West 3Rd. Street Suite #302, Long Beach, CA 90802
Website: espritv8.com
Lee Z. Wang
President
FLASHSILICON, INC
Business Services at Non-Commercial Site
1111 Ranchwood Pl, Diamond Bar, CA 91765
Lee Wang
Owner
TIME RIVER, INC
Ret Gifts/Novelties Ret Misc Merchandise
140 W Vly Blvd #123, San Gabriel, CA 91776
(626) 312-9679
Lee Wang
Principal
Ucla Computer Science Department
Computer Related Services
3732 Boelter Hall, Los Angeles, CA 90095
(310) 825-7879
Lee Wang
Finance, Purchasing Director
Rosemead School District
Elementary/Secondary School
3720 Rio Hondo Ave, Rosemead, CA 91770
(626) 443-4015
Lee Wang
Osteopathy, Partner
S M F Medicine
Medical Doctor's Office
Lee Wang
Neonatologist Perinatologist
Suburban Maternal Fetal Medici
Medical Doctor's Office
Lee Yu Wang
President
K. Wang Company Inc
1820 S Almansor St, Alhambra, CA 91801

Publications

Amazon

Technology in Education. Technology-Mediated Proactive Learning: Second International Conference, ICTE 2015, Hong Kong, China, July 2-4, 2015, Revised ... in Computer and Information Science)

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This book constitutes extended papers from the Second International Conference on Technology in Education, ICTE 2015, held in Hong Kong, China, in July 2015. The 26 full papers presented in this volume were carefully reviewed and selected from 41 submissions. They were organized in topical sections...
Binding

Paperback

Pages

293

Publisher

Springer

ISBN #

3662489775

EAN Code

9783662489772

ISBN #

4

Korean For Dummies

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Start speaking Korean the fun and easy way with Korean For Dummies, a no-nonsense guide to Korean culture and the basics of Korean language. Pick up basic phrases and commonly used words so that you can converse with Koreans in both business and personal situations. You’ll learn Korean for everyday ...
Author

Jungwook Hong

Binding

Paperback

Pages

384

Publisher

For Dummies

ISBN #

0470037180

EAN Code

9780470037188

ISBN #

3

Artificial Intelligence and Computational Intelligence: International Conference, AICI 2009, Shanghai, China, November 7-8, 2009, Proceedings (Lecture ... / Lecture Notes in Artificial Intelligence)

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The 2009 International Conference on Artificial Intelligence and Computational Int- ligence (AICI 2009) was held during November 7–8, 2009 in Shanghai, China. The technical program of the conference reflects the tremendous growth in the fields of artificial intelligence and computational intelligenc...
Binding

Paperback

Pages

737

Publisher

Springer

ISBN #

3642052525

EAN Code

9783642052521

ISBN #

5

Us Patents

Bit Symbol Recognition Method And Structure For Multiple Bit Storage In Non-Volatile Memories

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US Patent:
7400527, Jul 15, 2008
Filed:
Mar 16, 2006
Appl. No.:
11/378074
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
Flashsilicon, Inc. - Diamond Bar CA
International Classification:
G11C 16/04
US Classification:
36518503, 36518518, 36518519, 36518528
Abstract:
Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.

Structures And Methods To Store Information Representable By A Multiple Bit Binary Word In Electrically Erasable, Programmable Read-Only Memories (Eeprom)

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US Patent:
7515465, Apr 7, 2009
Filed:
Jun 7, 2006
Appl. No.:
11/449223
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
FlashSilicon Incorporation - Diamond Bar CA
International Classification:
G11C 16/04
US Classification:
36518503, 36518505, 36518519, 36518529, 257315
Abstract:
Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply. Using the distinctive threshold voltage associated with the different stored charges, the output voltage from the drain is distinctively recognized and converted back to the original n-bit word.

Bit-Symbol Recognition Method And Structure For Multiple-Bit Storage In Non-Volatile Memories

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US Patent:
7606069, Oct 20, 2009
Filed:
Apr 30, 2008
Appl. No.:
12/113117
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
FlashSilicon Incorporation - Diamond Bar CA
International Classification:
G11C 16/04
US Classification:
36518503, 36518518, 36518519, 36518528
Abstract:
Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.

Level Verification And Adjustment For Multi-Level Cell (Mlc) Non-Volatile Memory (Nvm)

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US Patent:
7626868, Dec 1, 2009
Filed:
May 4, 2007
Appl. No.:
11/744811
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
FlashSilicon, Incorporation - Diamond Bar CA
International Classification:
G11C 16/00
US Classification:
36518522, 36518503
Abstract:
Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a ‘gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy.

Level Verification And Adjustment For Multi-Level Cell (Mlc) Non-Volatile Memory (Nvm)

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US Patent:
7660154, Feb 9, 2010
Filed:
Dec 24, 2008
Appl. No.:
12/343945
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
FlashSilicon, Incorporation - Diamond Bar CA
International Classification:
G11C 16/00
US Classification:
36518503, 36518505
Abstract:
Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy.

Self-Adaptive And Self-Calibrated Multiple-Level Non-Volatile Memories

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US Patent:
7729165, Jun 1, 2010
Filed:
Mar 29, 2007
Appl. No.:
11/693610
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
FlashSilicon, Incorporation - Diamond Bar CA
International Classification:
G11C 11/34
US Classification:
36518503, 36518524
Abstract:
Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell.

Method And Structures For Highly Efficient Hot Carrier Injection Programming For Non-Volatile Memories

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US Patent:
7733700, Jun 8, 2010
Filed:
Jul 18, 2007
Appl. No.:
11/779838
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
Flashsilicon, Inc. - Diamond Bar CA
International Classification:
G11C 11/34
US Classification:
36518518, 36518519, 36518524, 36518526, 36518527, 36518528, 36518529, 36518533
Abstract:
A method programs a memory cell by controlling a reverse bias voltage across the PN junction between a source electrode of a MOSFET in the memory cell and the substrate, and pulling back the pinch-off point of the inversion region toward the source electrode, thereby increasing the programming efficiency of the memory cell. The method applies the main positive supply voltage Vto, the drain electrode of the memory cell from the chip main voltage supply, rather than the conventional method of using a higher voltage than V. To optimize the programming condition, the source voltage and the substrate voltage are adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i. e. using the gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage). The substrate voltage to the drain voltage can not exceed the avalanche multiplication junction breakdown for a small programming current during the bias voltage adjustment.

Methods And Structures For Reading Out Non-Volatile Memory Using Nvm Cells As A Load Element

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US Patent:
7859903, Dec 28, 2010
Filed:
Feb 14, 2008
Appl. No.:
12/031691
Inventors:
Lee Wang - Diamond Bar CA, US
Assignee:
FlashSilicon, Inc. - Diamond Bar CA
International Classification:
G11C 16/04
US Classification:
36518517, 36518511
Abstract:
A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.
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Lee Zhung Wang from Diamond Bar, CA, age ~64 Get Report