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Lan Gui Yu

from Oakland, CA

Lan Yu Phones & Addresses

  • 270 13Th St, Oakland, CA 94612
  • 270 13Th St APT 314, Oakland, CA 94612

Resumes

Resumes

Lan Yu Photo 1

Lan Yu

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Lan Yu Photo 2

Principle Application Engineer At Oracle

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Position:
Principle Application Engineer at Oracle
Location:
San Francisco Bay Area
Industry:
Computer Software
Work:
Oracle
Principle Application Engineer

Siebel Systems 2001 - 2006
Senior Software Engineer
Lan Yu Photo 3

Lan Yu

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Location:
United States
Lan Yu Photo 4

Lab Manager At Genentech

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Location:
San Francisco Bay Area
Industry:
Biotechnology

Business Records

Name / Title
Company / Classification
Phones & Addresses
Lan Yu
President
GM INNOVATION, INC
4691 Rousillon Ave, Fremont, CA 94555
38555 Salinger Ter, Fremont, CA 94536

Publications

Us Patents

Methods Of Forming Semiconductor Structures

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US Patent:
20230015781, Jan 19, 2023
Filed:
Jul 15, 2021
Appl. No.:
17/376504
Inventors:
- Santa Clara CA, US
Seshadri Ganguli - Sunnyvale CA, US
Lan Yu - Voorheesville NY, US
Siddarth Krishnan - Newark CA, US
Srinivas Gandikota - Santa Clara CA, US
Jacqueline S. Wrench - San Jose CA, US
Yixiong Yang - Fremont CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 29/45
H01L 29/40
H01L 21/285
H01L 21/324
Abstract:
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

Wikipedia References

Lan Yu Photo 5

Lan Yu

About:
Died:

1393

Work:
Position:

Tutor

Education:
Specialty:

Leader

Skills & Activities:
Master status:

Subordinate • Crown prince • Prince • Empress

Preference:

Rebel • Treason

Military rank:

Commander

Skill:

LAN

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