Lan D Lee

6430067, Aug 6, 2002

Apr 12, 2001

09/834155

Lan Lee - Palo Alto CA

Sun Microsystems, Inc. - Palo Alto CA

H02M 318

363 60

A method and apparatus for a voltage multiplier is disclosed that includes a first stage for receiving an input voltage and a first control signal; inverting the first control signal to produce a second control signal; and outputting a first output voltage and the second control signal. The voltage multiplier also includes a second stage for receiving the first output voltage and the second control signal; and outputting a third output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.

6493790, Dec 10, 2002

Jan 30, 1998

09/016207

Cong Khieu - San Jose CA
Xin Liu - Sunnyvale CA
Der-ren Chu - San Jose CA
Lan Lee - Palo Alto CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1210

711108, 711202, 711206, 36518907

A translation-lookaside buffer includes a content-addressable memory (CAM) cell to generate a CAM current signal with a first transistor configuration having a set of transistors of a predetermined size and connection. A reference current circuit generates a reference current signal with a second transistor configuration corresponding to the first transistor configuration, with the exception of the size and connection of selected transistors. A match sense amplifier selectively generates a match signal in response to the CAM current signal and the reference current signal.

6865098, Mar 8, 2005

May 30, 2003

10/449422

Michael Edwin Ichiriu - Sunnyvale CA, US
Masaru Shinohara - Fremont CA, US
YueFei Ge - San Jose CA, US
Lan Lee - Palo Alto CA, US

NetLogic Microsystems, Inc. - Mountain View CA

G11C015/00

365 49, 365200, 36518907

A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

6900674, May 31, 2005

Feb 27, 2003

10/375587

Massimo Sutera - Sunnyvale CA, US
Daniel Y. Cheung - Cupertino CA, US
Lan Lee - Palo Alto CA, US
Kevin B. Normoyle - Santa Clara CA, US
Sung-Hun Oh - Sunnyvale CA, US
Ivana Capellano - Palermo, IT

Sun Microsystems, Inc. - Santa Clara CA

H03L007/00

327144, 327160

In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.

20120176125, Jul 12, 2012

Jan 12, 2011

13/005007

Lan Lee - Palo Alto CA, US
Shanshan Lee - Palo Alto CA, US

G01B 7/30
H02K 7/18
G01B 11/26

32420725, 35613909, 290 1 R

A device for sensing positions of a rotating wheel comprises a rotating wheel with a symmetrical weight distribution, with the rotating wheel being rigidly attached to an axle; a stationary plate coaxial with the rotating wheel, the stationary plate being free to rotate about the axle and having an asymmetrical weight distribution to keep the stationary plate stationary due to the forces of gravity; and a position sensor to sense positions of the rotating wheel.

20120306327, Dec 6, 2012

Jun 2, 2011

13/151824

Lan Lee - Palo Alto CA, US
Shanshan Lee - Palo Alto CA, US

B62J 6/12
H02K 7/18

310 67 A

Provided are electricity generating bicycle wheel assemblies configured to generate electrical power. In certain embodiments, an electricity generating bicycle wheel assembly includes a hub, and an axle protruding through and rotatably attached to the hub, such that the axle is configured to rigidly attach to a bicycle frame on each side of the hub. The assembly also includes an electrical generator positioned within the hub and rigidly attached to the axle. The electrical generator includes a generator axle rotatably coupled to the hub such that rotation of the hub with respect to the axle facilitates rotation of the generator axle with respect to the electrical generator.

61218715, Sep 19, 2000

Mar 1, 1999

9/260583

Lan Lee - Palo Alto CA
Cong Khieu - San Jose CA

Sun Microsystems, Inc. - Palo Alto CA

G05B 100

3401462

A circuit for comparing two digital words has a set of bit compare circuits that generate a set of compare signals. Each bit compare circuit receives a first bit from a first digital word and a corresponding bit from a second digital word and generates one compare signal that indicates a match between the first bit and the corresponding bit. In response to the set of compare signals, a composite match detector circuit generates a composite match signal. A last bit detector circuit generates a last bit signal that indicates a match between a last bit from the first digital word and a last bit from the second digital word. When the last bit signal is received, a match hit generator circuit generates a match hit signal based on the composite match signal and the last bit signal.

61631922, Dec 19, 2000

Feb 26, 1999

9/259148

Lan Lee - Palo Alto CA
Hiep P. Ngo - Sunnyvale CA
Cong Khieu - San Jose. CA

Sun Microsystems, Inc. - Palo Alto CA

H03K 3356

327212

A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.