Kyu Sung Min

7498655, Mar 3, 2009

Mar 28, 2006

11/392102

Kyu S. Min - San Jose CA, US
Nathan R. Franklin - San Mateo CA, US

Intel Corporation - Santa Clara CA

H01L 29/00

257530, 257528, 257529, 369 1301, 369 1302

Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.

7585564, Sep 8, 2009

Feb 13, 2007

11/706730

Jeffery A. Whiteford - Belmont CA, US
Mihai Buretea - San Francisco CA, US
William P. Freeman - San Mateo CA, US
Andreas Meisel - San Francisco CA, US
Kyu S. Min - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US
Erik Scher - San Francisco CA, US

Nanosys, Inc. - Palo Alto CA

B32B 5/66

428402, 428403, 428404, 428405, 428406, 428407, 427212, 427384

Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.

7705389, Apr 27, 2010

Aug 29, 2007

11/847183

Ron Weimer - Boise ID, US
Kyu Min - San Jose CA, US
Tom Graettinger - Boise ID, US
Nirmal Ramaswamy - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 29/788

257314, 257321, 257E29304

Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

7750433, Jul 6, 2010

Feb 12, 2009

12/370450

Kyu S. Min - San Jose CA, US
Nathan R. Franklin - San Mateo CA, US

Intel Corporation - Santa Clara CA

H01L 29/00

257529, 257528, 257530, 369126, 369127

Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.

7763511, Jul 27, 2010

Dec 29, 2006

11/618666

Prashant Majhi - Austin TX, US
Kyu S. Min - San Jose CA, US
Wilman Tsai - Saratoga CA, US

Intel Corporation - Santa Clara CA

H01L 21/00

438257, 438260, 438710

Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.

7773493, Aug 10, 2010

Sep 29, 2006

11/540271

Kyu Min - San Jose CA, US
Qing Ma - San Jose CA, US
Nathan R. Franklin - San Mateo CA, US

Intel Corporation - Santa Clara CA

G11B 9/00
G11C 13/04
G11C 13/00

369126, 365110, 365151, 257530

In one embodiment, the present invention includes an apparatus having a conductive storage medium to store information in the form of electrostatic charge. The conductive storage medium can be disposed in a non-conductive layer that is formed over a charge blocking layer, which in turn may be disposed over an electrode layer. In one embodiment, a barrier layer may be disposed over the non-conductive layer. Other embodiments are described and claimed.

7795607, Sep 14, 2010

Sep 29, 2006

11/529830

Kyu S. Min - San Jose CA, US
Nathan R Franklin - San Mateo CA, US

Intel Corporation - Santa Clara CA

H01L 29/76
H01L 47/00

257 4, 257 2, 257 3, 257 5, 257E27004, 257E31008, 257E31029, 257E45002, 438 95, 438 96, 369126

An apparatus comprising a substrate, an electrode coupled to the substrate, a modifiable layer coupled to the electrode, and a current focusing layer coupled to the modifiable layer. The current focusing layer comprises a conductive region and an insulating region. A method comprising forming a modifiable layer on an electrode and forming a current focusing layer on the modifiable layer.

7898850, Mar 1, 2011

Oct 12, 2007

11/871339

Kyu S. Min - San Jose CA, US
Rhett T. Brewer - Santa Clara CA, US
Tejas Krishnamohan - Palo Alto CA, US
Thomas M. Graettinger - Boise ID, US
D. V. Nirmal Ramaswamy - Boise ID, US
Ronald A. Weimer - Boise ID, US
Arup Bhattacharyya - Essex Junction VT, US

Micron Technology, Inc. - Boise ID

G11C 11/34

36518503, 36518528, 977943

Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.