Inventors:
Chung Wai Leung - Milpitas CA, US
Jin-Ho Kim - Cupertino CA, US
Kwok Kwok Ng - Morgan Hill CA, US
Assignee:
ProMOS Technologies Inc. - Hsin Chu
International Classification:
H01L 27/115
H01L 29/66
US Classification:
257316, 257320, 257E27103, 257E29304, 257E21682, 438257, 438258, 438259
Abstract:
A memory cell () has a plurality of floating gates (L, R). The channel region () comprises a plurality of sub-regions (L, R) adjacent to the respective floating gates, and a connection region () between the floating gates. The connection region has the same conductivity type as the source/drain regions () to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric () becomes thick between the floating gates, weakening the control gate's () electrical field in the channel.