Kwok Choi Ng

6395611, May 28, 2002

Nov 1, 1999

09/432725

Nathan Belk - Scotch Plains NJ
William Thomas Cochran - Clermont FL
Michel Ranjit Frei - Berkeley Heights NJ
David Clayton Goldthorp - Reiffton PA
Shahriar Moinian - New Providence NJ
Kwok K. Ng - Warren NJ
Mark Richard Pinto - Summit NJ
Ya-Hong Xie - Beverly Hills CA

Agere Systems Guardian Corp. - Orlando FL

H01L 2120

438381, 438383

An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

6509242, Jan 21, 2003

Jan 12, 2001

09/759120

Michel Ranjit Frei - Berkeley Heights NJ
Clifford Alan King - New York NY
Yi Ma - Orlando FL
Marco Mastrapasqua - Annandale NJ
Kwok K Ng - Warren NJ

Agere Systems Inc. - Allentown PA

H01L 21331

438312, 438360, 257200, 257565, 257586

A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

7180103, Feb 20, 2007

Sep 24, 2004

10/948897

Jeff D. Bude - New Providence NJ, US
Peide Ye - High Bridge NJ, US
Kwok K. Ng - Warren NJ, US
Bin Yang - Bridgewater NJ, US

Agere Systems Inc. - Allentown PA

H01L 29/739
H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 31/109

257200, 257 11, 257189, 257201

A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

H289, Feb 3, 1987

Feb 17, 1984

6/581336

Kwok K. Ng - Union NJ
Simon M. Sze - Berkeley Heights NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2316
H01L 2904
H01L 2100

357 75

One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

47631830, Aug 9, 1988

Oct 24, 1986

6/921899

Kwok K. Ng - Union NJ
Simon M. Sze - Berkeley Heights NJ

American Telephone and Telegraph Co., AT&T Bell Laboratories - Murray Hill NJ

H01L 2978
H01L 2712
H01L 2980
H01L 2948

357 237

A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e. g. , IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e. g. , a mask, which, in terms of the pattern it produces, is substantially identical to a second pattern delineating device.

57448400, Apr 28, 1998

Nov 20, 1995

8/560671

Kwok Kwok Ng - Berkeley Heights NJ

H01L 2362

257360

Protecting device structures are disclosed for protecting one or more protected nodes of an integrated circuit to be protected against electrostatic discharges (ESD). Typically the integrated circuit includes n channel MOS transistors having terminals connected to the protected nodes. In a specific embodiment, the protecting device structure includes an MOS diode structure having source and drain regions and at least a pair of localized auxiliary region. Each of this pair of localized auxiliary regions has a conductivity type that is opposite from that of the source and drain regions. These localized auxiliary regions are located contiguous with the source and drain regions, respectively, and in the channel between the source and drain regions. The protecting device structure is integrated in the integrated circuit and has a terminal that is connected to a terminal of each of the one or more protected nodes of the integrated circuit.

46138919, Sep 23, 1986

Feb 17, 1984

6/581259

Kwok K. Ng - Union NJ
Simon M. Sze - Berkeley Heights NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2348
H01L 2944
H01L 2952

357 68

One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

51344475, Jul 28, 1992

Aug 27, 1990

7/574564

Kwok K. Ng - Berkeley Heights NJ
Chien-Shing Pai - Bridgewater NJ

AT&T Bell Laboratories - Murray Hill NJ

H01L 2910

357 234

In order to reduce the rate of (hot charge-carrier) degradation of semiconductor devices formed in a semiconductor body, a neutral impurity--such as germanium in silicon MOS transistors--is introduced into the body in a neighborhood of an intersection of a p-n junction with a surface of the body.