Search

Kin Fai Ma

from Boise, ID
Age ~65
Get Report
Also known as:
Kin F Ma, Kin Manny Ma, Manny K Ma, Ma Kin Fai, Manny W Ma, Kin Fma, Kin Fai, Kim Ma
Phone and address:
2427 Gloucester St, Boise, ID 83706
(208) 368-0898
Related to:
Kearia K Rabun, 34Cornett King, 59Carol HosmanRussell Olson, 71Matthew Hosman
Connected to:
Aileen F Ma, 33Alex Ma, 36Alexander C Ma, 76Aliza X Ma, 38Anila T Ma, 42Anny S Ma, 57Arick C Ma, 51Arleen C Ma, 49Bao P Ma, 73Barry K Ma, 69

Kin Ma Phones & Addresses

  • 2427 Gloucester St, Boise, ID 83706 (208) 368-0898
  • Coppell, TX
  • Federal Heights, CO

Publications

Us Patents

Material Removal Method For Forming A Structure

View page
US Patent:
6461967, Oct 8, 2002
Filed:
Jul 16, 2001
Appl. No.:
09/907296
Inventors:
Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2100
US Classification:
438705, 216 38, 216 87, 438692, 438753
Abstract:
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Method For Reducing Capacitive Coupling Between Conductive Lines

View page
US Patent:
6570258, May 27, 2003
Filed:
Jun 18, 2001
Appl. No.:
09/884630
Inventors:
Kin F. Ma - Boise ID
Eric T. Stubbs - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2940
US Classification:
257774, 257208, 257758, 257773, 257776, 257907
Abstract:
An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

Material Removal Method For Forming A Structure

View page
US Patent:
6596642, Jul 22, 2003
Filed:
Jul 11, 2002
Appl. No.:
10/193801
Inventors:
Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2100
US Classification:
438705, 216 38, 216 87, 438692, 438753
Abstract:
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Material Removal Method For Forming A Structure

View page
US Patent:
6596648, Jul 22, 2003
Filed:
Jul 11, 2002
Appl. No.:
10/193850
Inventors:
Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2100
US Classification:
438745, 438692, 438756
Abstract:
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Material Removal Method For Forming A Structure

View page
US Patent:
6599840, Jul 29, 2003
Filed:
Jul 11, 2002
Appl. No.:
10/194833
Inventors:
Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2100
US Classification:
438705, 438752, 438753
Abstract:
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Method For Reducing Capactive Coupling Between Conductive Lines

View page
US Patent:
62591622, Jul 10, 2001
Filed:
Sep 9, 1998
Appl. No.:
9/150628
Inventors:
Kin F. Ma - Boise ID
Eric T. Stubbs - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2940
H01L 2348
H01L 27108
US Classification:
257774
Abstract:
An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

Methods Of Making Implanted Structures

View page
US Patent:
63099756, Oct 30, 2001
Filed:
Mar 14, 1997
Appl. No.:
8/818660
Inventors:
Zhiqiang Wu - Meridian ID
Li Li - Meridian ID
Thomas A. Figura - Boise ID
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Boise ID
Kin F. Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2100
US Classification:
438705
Abstract:
Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material. One preferred selective etching process uses an etchant solution comprising a selected weight percentage of tetramethyl ammonium hydroxide in deionized water. The etchant solution etches relatively unimplanted silicon-containing material implanted up to 60 times faster than it etches silicon-containing material implanted to beyond a threshold concentration of ions.

Material Removal Method For Forming A Structure

View page
US Patent:
62619640, Jul 17, 2001
Filed:
Dec 4, 1998
Appl. No.:
9/205989
Inventors:
Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2100
US Classification:
438705
Abstract:
Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
Control profile
Kin Fai Ma from Boise, ID, age ~65 Get Report