Ki Soo Kang

7052525, May 30, 2006

Aug 13, 2003

10/639500

Ki Ho Kang - Fairfax VA, US
Boyd Lease - Melbourne FL, US

Ensco, Inc. - Springfield VA

B01D 53/04
F25D 9/00
H01J 49/40

553852, 95 95, 95148, 95273, 96397, 96405, 96417, 250287, 250288, 250366, 250361 R, 73 234, 356301

A protective system having an upstream detection subsystem to detect a contaminant in an airflow and to provide a contaminant signal, an upstream detection subsystem, a filtration subsystem to filter the contaminant from the airflow, a valve adapted to allow selective routing of the airflow, and a control system adapted to control the valve to route the airflow through the protective system upon receiving the contaminant signal from the upstream detection subsystem. In one embodiment, the upstream detection subsystem includes at least two different types of detectors for detecting same type of contaminants. In another embodiment, the upstream detection subsystem is adapted to detect a contaminant, and a daughter compound. In another embodiment, the protective system includes a downstream detection subsystem. In yet another embodiment, the protective system includes a vehicle data link subsystem.

56664850, Sep 9, 1997

Jun 7, 1995

8/474174

Gananathan Suresh - Potomac MD
Ki B. Kang - Centreville VA
Young Il Kim - Gaithersburg MD

Samsung Electronics Inc. - Ridgefield Park NJ

G06F 1300

39518501

In a system bus having a master-slave architecture, shared memory controlled by a plurality of registers, master-slave central processing units, and master-slave bus controllers, a process of reading and writing data to the shared memory is disclosed. The process comprises the steps of requesting access to the shared memory by the central processing units by writing a request bit on a first register; reading an access bit on a second register to determine whether the access bit is set and access to shared memory is granted; reading or writing data to the shared memory by the central processing units; and reading the access bit on the second register to determine whether the access bit is cleared and access to the shared memory is complete. The access bit is set by the master-slave bus controller.

60001259, Dec 14, 1999

Apr 30, 1998

9/069994

Ki B. Kang - Centreville VA

Samsung Electronics America, Inc. - Ridgefield Park NJ

H05K 330

29832

A natural heat dissipation device for a microprocessor. The microprocessor is conventionally mounted to a printed circuit board. The printed circuit board contains a recess that is cut-out directly below the microprocessor. Heat sink material is attached to the microprocessor through the recess. The heat sink material attached to the bottom of the microprocessor may be used alone or in conjunction with a an attached metal tray or case under the printed circuit board.

57903794, Aug 4, 1998

Nov 5, 1997

8/968848

Ki B. Kang - Centreville VA

Samsung Electronics America, Inc. - Ridgefield Park NJ

H05K 720

361719

A natural heat dissipation device for a microprocessor. The microprocessor is conventionally mounted to a printed circuit board. The printed circuit board contains a recess that is cut-out directly below the microprocessor. Heat sink material is attached to the microprocessor through the recess. The heat sink material attached to the bottom of the microprocessor may be used alone or in conjunction with a an attached metal tray or case under the printed circuit board.

59601957, Sep 28, 1999

Jun 3, 1996

8/657423

Ki B. Kang - Centreville VA
Michael Gilbert - Germantown MD

Samsung Electronics Co., Ltd. - Suwon

G06F 9445

395651

A volatile memory initialization systems differentiates between a first class of reset causes requiring memory initialization and a second class of reset causes not requiring memory initialization. A register records the first and second classes of reset causes. A volatile memory initialization function is performed when a reset of the first class of reset causes is read from the register. The volatile memory initialization function is bypassed when a reset of the second class of reset causes is read from the register.

58569219, Jan 5, 1999

Jun 7, 1995

8/482396

Young Il Kim - Gaithersburg MD
Ki B. Kang - Centreville VA
Young C. Cheon - Gaithersburg MD
Jong Ky Lee - Gaithersburg MD

Samsung Electronics Co., Ltd. - Suwon

G05B 1500

364132

A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master system processor module is coupled to the backplane bus via a master bus controller. The master system processor module contains a central processing unit in selective communication the master bus controller. A plurality of slave modules are also coupled to the backplane bus via respective slave bus controllers. Each of the slave modules has a slave central processing unit in selective communication the slave bus controller. The master and slave bus controllers are in selective communication with the bus memory, the plurality of control registers, and the respective central processing units, to transmit and receive data through the backplane bus.

58450971, Dec 1, 1998

Jun 3, 1996

8/657371

Ki B. Kang - Centreville VA
Dae S. Kang - Gaithersburg MD

Samsung Electronics Co., Ltd. - Suwon

G06F 13362

395297

A bus recovery system for multi-master bus system comprises a plurality of bus masters selectively interfacing with a system bus whereby access to the bus is controlled by a bus arbiter. A plurality of counters corresponding to each of the plurality of masters contains a pre-determined time value corresponding to the maximum time each of the plurality of masters may be granted access to bus. The arbiter releases ownership of the bus when the pre-determined time value in the counter has been exceeded by master currently accessing the bus. A register identifies which of the masters had access to the bus when the predetermined time value was exceeded.