Ken K Ye

6856557, Feb 15, 2005

May 30, 2003

10/452562

Johnny Chan - Fremont CA, US
Jinshu Son - Saratoga CA, US
Ken Kun Ye - Fremont CA, US
Tinwai Wong - Fremont CA, US

Atmel Corporation - San Jose CA

G11C011/34

365190, 365233

A signal integrity checking circuit for an integrated circuit detects whether signal condition involving loading of data into storage elements is valid or improper and flags the result. The integrity circuit includes a plurality of adjacently positioned and substantially similar storage elements, which are clocked by a common clock line and loaded from a common data input line. A common reset line may also be provided. The storage elements may be flip-flops, latches, RAM, etc. A logic gate, such as a NAND gate, receives the storage element outputs and flags improper loading of data. Inverters on the input and output sides of one storage element force it to the opposite state from the other storage element. The signal integrity checking circuit is valuable for ensuring proper loading during power-on or start-up, and at other times when loading of data may occur.

7279961, Oct 9, 2007

Nov 21, 2005

11/284780

Johnny Chan - Fremont CA, US
Tin Wai Wong - Fremont CA, US
Ken Kun Ye - Fremont CA, US

Atmel Corporation - San Jose CA

G05F 1/10
G05F 3/02

327540, 327536, 363 60

A charge pump generates a voltage higher than an intermediate voltage and a regulator circuit provides a first regulated voltage higher than the intermediate voltage. A second stage includes a regulator stage using the first voltage to provide the intermediate voltage from the first voltage. A charge pump provides a pump output voltage. The pump output voltage is divided and the divided voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.

7782240, Aug 24, 2010

May 29, 2007

11/754879

Philip S. Ng - Cupertino CA, US
Ken Ye - Fremont CA, US

Atmel Corporation - San Jose CA

H03M 1/12

341155, 370447

A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from the single-wire interface at a power-supply voltage level and charges the charge storage device to the same level. Non-communication periods produce a charging period sufficient for the charge storage device to attain the power-supply voltage level.

6815992, Nov 9, 2004

Jun 25, 2003

10/607286

Philip S. Ng - Cupertino CA
Ken Kun Ye - Fremont CA
Jinshu Son - Saratoga CA

Atmel Corporation - San Jose CA

H03K 3037

327199, 327407

A switch controlling circuit for the testing and fine-tuning of integrated circuits comprising of a series of flip-flops chain together in a serial manner. The contents of the flip-flop are shift in from the input of the first flip-flop in the chain. The output of each flip-flop connects to individual switch whereby the states of the flip-flops control the state of the switches.